docs: explain pin-header mating-side aliases

[zenoutlabs]

The pin-header reference omits connectsFromAbove and connectsFromBelow, even though the props schema supports them. Document the two mating-side aliases, explicit layer precedence, false values, and the error when both aliases are true. A runnable PCB comparison places one header on each side of the board and distinguishes board-side selection from footprint inversion.

Part of #849, track 8 only. This independently written update follows the unmerged documentation attempts in #854 and #874, using the current props schema and its existing tests as the source of truth.

Validation:

• Documentation format check, typecheck, production build, and git diff --check pass. The format check runs before generated Docusaurus output is present, as in a clean checkout.
• The exact new preview builds with tscircuit@0.0.2553 / CLI 0.1.2255; emitted PCB components put J_TOP on top and J_BOTTOM on bottom. PCB and schematic images render. Its intentionally unconnected headers produce missing-trace warnings, plus the existing missing-sheet warning.
• Independent review checked the alias contract, explicit precedence, invalid combinations, and the exact preview against the generated circuit.
• The hosted PCB renderer displays top-side J_TOP and mirrored bottom-side J_BOTTOM silkscreen from the exact example source. The comparison hides its 3D tab because the current CAD preview depicts both headers above the board despite the correct PCB layers. No CAD data or runtime behavior is changed.

Preview: pin-header reference. Verified the deployed page, the expanded PCB comparison with mirrored bottom-side silkscreen, and the hidden 3D tab.

Prepared with OpenAI Codex assistance and validated locally. No runtime or dependency changes.

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Project	Deployment	Actions	Updated
docs	Ready	Preview	Oct 8, 2026 7:17pm UTC