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Add side net-label alignment solver#682

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mohan-bee wants to merge 2 commits into
tscircuit:mainfrom
mohan-bee:feat-01
Draft

Add side net-label alignment solver#682
mohan-bee wants to merge 2 commits into
tscircuit:mainfrom
mohan-bee:feat-01

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@mohan-bee

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Adds a final schematic-trace solver that groups horizontal child net labels on each chip side into one aligned column and creates short connector traces to preserve their connections. This gives nearby components more routing space, keeps side connections readable, and includes a PCA9306 repro with regression snapshots.

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vercel Bot commented Jul 17, 2026

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Project Deployment Actions Updated (UTC)
schematic-trace-solver Ready Ready Preview, Comment Jul 17, 2026 8:19am

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