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FPGA Gate FPGA Gate #39: Manually run by tinebp
6h 11m 40s master
master
6h 11m 40s
CP regfile Fmax, early-Z fix + default on, asic_gate 4x4 top/gfx, CI … CI #1912: Commit 9643f3e pushed by tinebp
2h 34m 44s master
master
2h 34m 44s
CP regfile Fmax, early-Z fix + default on, asic_gate 4x4 top/gfx, CI shards + ccache CI #1911: Pull request #425 opened by tinebp
2h 43m 54s ci-earlyz-asic-gate
ci-earlyz-asic-gate
2h 43m 54s
ci: re-record the fpga_gate top and gfx baselines CI #1910: Commit 62aaa31 pushed by tinebp
7m 19s ci-earlyz-asic-gate
ci-earlyz-asic-gate
7m 19s
fpga_figures: core-submodule placement/routing views and area breakdo… CI #1909: Commit 42c2a4f pushed by NikhilRout
34s feature_mx
feature_mx
34s
FPGA Gate FPGA Gate #38: Manually run by tinebp
6h 7m 26s master
master
6h 7m 26s
CI CI #1908: Scheduled
4h 49m 20s master
master
4h 49m 20s
ASIC Gate ASIC Gate #33: Scheduled
1h 40m 7s master
master
1h 40m 7s
ci: probe the toolchain cache under the key it is saved with CI #1907: Commit 3c3a84b pushed by tinebp
1h 34m 56s master
master
1h 34m 56s
ci: gate top, gfx, tensor and vm in asic_gate at NT=NW=8 CI #1906: Commit 4966e76 pushed by tinebp
34m 30s master
master
34m 30s
ci: refresh the gfx_draw3d references and perf baselines after Vulkan rt CI #1905: Commit 8524ae6 pushed by tinebp
5h 10m 9s master
master
5h 10m 9s
cache: keep an order-demoted store out of the data array until its re… CI #1904: Commit 5b4eec9 pushed by tinebp
1h 43m 26s master
master
1h 43m 26s
Vulkan rt (#424) CI #1902: Commit 6f372b0 pushed by tinebp
22m 47s master
master
22m 47s
Vulkan rt CI #1901: Pull request #424 opened by tinebp
52m 55s vulkan-rt
vulkan-rt
52m 55s
vxbin: read kernel entries from readelf columns, not a decimal-size p… CI #1900: Commit 833a108 pushed by tinebp
4m 15s vulkan-rt
vulkan-rt
4m 15s
ci: add a wide-issue suite at the default execution-block count CI #1899: Commit 61ddbac pushed by tinebp
58m 28s master
master
58m 28s
FPGA Gate FPGA Gate #37: Manually run by tinebp
5h 24m 33s master
master
5h 24m 33s
ASIC Gate ASIC Gate #32: Scheduled
20m 29s master
master
20m 29s
simx: model the issue lock, per-slot dispatch queues and port-0 flush… CI #1898: Commit 5eec172 pushed by tinebp
5h 18m 52s master
master
5h 18m 52s
simx: model the issue lock, per-slot dispatch queues and port-0 flush register as the RTL builds them CI #1897: Pull request #423 synchronize by tinebp
7m 9s simx-parity-issue-lock
simx-parity-issue-lock
7m 9s
Merge branch 'master' into simx-parity-issue-lock CI #1896: Commit 529458f pushed by tinebp
7m 19s simx-parity-issue-lock
simx-parity-issue-lock
7m 19s
afu: route the command processor through the bank adapter on multi-po… CI #1895: Commit f63adcf pushed by tinebp
7m 43s master
master
7m 43s
simx: model the issue lock, per-slot dispatch queues and port-0 flush register as the RTL builds them CI #1894: Pull request #423 synchronize by tinebp
3m 47s simx-parity-issue-lock
simx-parity-issue-lock
3m 47s
ci: run the synthesis gates only on nights that follow a synthesis-in… CI #1893: Commit aa23cad pushed by tinebp
20s simx-parity-issue-lock
simx-parity-issue-lock
20s
simx: model the issue lock, per-slot dispatch queues and port-0 flush register as the RTL builds them CI #1892: Pull request #423 opened by tinebp
5m 25s simx-parity-issue-lock
simx-parity-issue-lock
5m 25s