fix(t27b): fold a constant rst_n/en tie-off out of the clocked process (Closes #10046)

.trinity/seals/t27b_T27bAstShape.json

@@ -1,13 +1,13 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+cc19d1fcd",
+  "built_by": "t27c-bootstrap@0.5.2+f787afb",
   "closure": [
     {
       "spec": "specs/tri/t27b/ast_scan.t27",
       "spec_hash": "sha256:e6f28b9bceb1b0fd5315e80a66beed3d791311dacf2bd5d5b7cbc79250d8b385"
     },
     {
       "spec": "specs/tri/t27b/verilog_plan.t27",
-      "spec_hash": "sha256:6178c276f6928f211b1cb65f470a93a5fcfbb11119bad7a26030072d777e8e70"
+      "spec_hash": "sha256:a52dbb4524173c54e19d205ee72b8a1544da978df82cc15a92341c7cad9ba428"
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
@@ -18,7 +18,7 @@
   "module": "T27bAstShape",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-11T10:43:29Z",
+  "sealed_at": "2026-10-17T17:33:08Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
   "spec_hash": "sha256:fef40e3e7885265523c48d4a936c033bbc929b80dbf3ec06f79332dd63834134",
   "spec_path": "specs/tri/t27b/ast_shape.t27",

.trinity/seals/t27b_T27bVerilogEmit.json

@@ -1,33 +1,33 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+cc19d1fcd",
+  "built_by": "t27c-bootstrap@0.5.2+f787afb",
   "closure": [
     {
       "spec": "specs/tri/t27b/text_escape.t27",
       "spec_hash": "sha256:c88981799b2e3f97cd0815471d288e48550f5a785c504412546ca58c0b19656a"
     },
     {
       "spec": "specs/tri/t27b/verilog_plan.t27",
-      "spec_hash": "sha256:6178c276f6928f211b1cb65f470a93a5fcfbb11119bad7a26030072d777e8e70"
+      "spec_hash": "sha256:a52dbb4524173c54e19d205ee72b8a1544da978df82cc15a92341c7cad9ba428"
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
-  "gen_hash_c": "sha256:83ed268b2738067a1d1010e8eb36c4074d0aebe3b9151be66794e47af3d90710",
-  "gen_hash_rust": "sha256:b711c621b7719f9446912c05d02e7bd0e03f41bee71472a2fcb91f98c6c75392",
-  "gen_hash_verilog": "sha256:484bc265025e26176a53aceccf7b23f64ced954fcc3c2d46911c6469b53b7bfc",
-  "gen_hash_zig": "sha256:0803344590f689a6601e8ff7f60c76da2162437623e69262f29e46f1bb1fb360",
+  "gen_hash_c": "sha256:e898398e1e6f1541b034d7f93b45eca4341c961f5b37ba1e154c02b3272ece5b",
+  "gen_hash_rust": "sha256:b218d53be59a034da8a84565c204e96647bcb1b7af9bd400d448149a9904ae31",
+  "gen_hash_verilog": "sha256:17511cc822f43fc37f070e9d2178ffa1ff1f6ef1300134a38cb9bdcab4e03d49",
+  "gen_hash_zig": "sha256:a654b907033a49164f3eb19c4592c1cf58ce7d7b29230819258712cdb7a00e41",
   "module": "T27bVerilogEmit",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-11T10:43:31Z",
+  "sealed_at": "2026-10-17T17:33:08Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
-  "spec_hash": "sha256:0cc23245474d6ce568497b119e5cd719673c7487c3544817af8ac49c7f960aa6",
+  "spec_hash": "sha256:62dfd9b10d4cbcb90a55ca2c76c712c9b94ffd8a416020ac1f8ff980b930ca60",
   "spec_path": "specs/tri/t27b/verilog_emit.t27",
   "tests": {
     "failed": 0,
     "failing": [],
     "forced": false,
-    "passed": 5,
-    "total": 5,
+    "passed": 7,
+    "total": 7,
     "vacuous": 0
   },
   "toolchain": {

.trinity/seals/t27b_T27bVerilogPlan.json

@@ -1,22 +1,22 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+67cbf8284",
+  "built_by": "t27c-bootstrap@0.5.2+f787afb",
   "closure": [
     {
       "spec": "specs/tri/t27b/ast_walk.t27",
       "spec_hash": "sha256:6653bee4e36f576c6b04d29b537ad52481c959e98b922257f48f3c0d4cf809e3"
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
-  "gen_hash_c": "sha256:07009024c2ece655f0c4b8547b2973a7e0453d3b2518cdf00cb8d9cf5455f7fd",
-  "gen_hash_rust": "sha256:94d020775bc80ba2eadfa1548da37b070cb08f54ee766f294cef05a5f10752cf",
-  "gen_hash_verilog": "sha256:238ce5f1e1849efe809f4e5a3804c7407a42fd37a1304e801c1ecb50c7412822",
-  "gen_hash_zig": "sha256:91d40b10511d2e8569c8e2eea0dfb53bc4ab3ac2b3a8c83b88b2108c57f8bf4c",
+  "gen_hash_c": "sha256:88edabc42fca646e9a444d9f82370d78ecb67a5afa554f949f57fb4eb573a7f4",
+  "gen_hash_rust": "sha256:b02233d200b6cad6d160305768928911509d98199f0aee9d208bf9f14a1e9065",
+  "gen_hash_verilog": "sha256:c490c6a07fb43b4ae5fd69949d9725baf10e9332277667b7365ce040d605280d",
+  "gen_hash_zig": "sha256:30a577020d433ae2de867124d570b67a3f4799d03909c83c38f3f723a33d3a55",
   "module": "T27bVerilogPlan",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-10T23:14:12Z",
+  "sealed_at": "2026-10-17T17:33:05Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
-  "spec_hash": "sha256:6178c276f6928f211b1cb65f470a93a5fcfbb11119bad7a26030072d777e8e70",
+  "spec_hash": "sha256:a52dbb4524173c54e19d205ee72b8a1544da978df82cc15a92341c7cad9ba428",
   "spec_path": "specs/tri/t27b/verilog_plan.t27",
   "tests": {
     "failed": 0,

gen/rust/tri/t27b/verilog_emit.rs

@@ -1,6 +1,6 @@
 // Generated from .t27 spec
 // DO NOT EDIT — generated by t27c
-// NOT LOWERED BY THIS BACKEND: 5 test(s), 0 invariant(s), 0 function(s) with no body.
+// NOT LOWERED BY THIS BACKEND: 7 test(s), 0 invariant(s), 0 function(s) with no body.
 // This backend emits declarations only. The spec's checks live in
 // the Zig and Verilog outputs; do not read this file as verified.
 
@@ -628,6 +628,24 @@ pub fn has_net(nodes: &[u8], text: &[u8], meta: &[u8], ptext: &[u8], name: &'sta
     return false;
 }
 
+pub fn folded_tie(nodes: &[u8], text: &[u8], meta: &[u8], ptext: &[u8], c: usize) -> bool {
+    if ((kind(nodes, c) != K_CONST_DECL) || (item_class(nodes, text, meta, ptext, c) != C_CONST)) {
+        return false;
+    }
+    return tie_folds(&text[(lo(nodes, c, F_NAME)) as usize..(hi(nodes, c, F_NAME)) as usize], fold_val(nodes, text, meta, ptext, 0, (c + 1), 0));
+}
+
+pub fn tied_on(nodes: &[u8], text: &[u8], meta: &[u8], ptext: &[u8], name: &'static str) -> bool {
+    let mut c: usize = 1;
+    while (c < end(nodes, 0)) {
+        if ((kind(nodes, c) == K_CONST_DECL) && field_eq(nodes, text, c, F_NAME, name)) {
+            return folded_tie(nodes, text, meta, ptext, c);
+        }
+        c = end(nodes, c);
+    }
+    return false;
+}
+
 pub fn declares_ports(nodes: &[u8], text: &[u8], meta: &[u8], ptext: &[u8]) -> bool {
     let mut c: usize = 1;
     while (c < end(nodes, 0)) {
@@ -2187,7 +2205,7 @@ pub fn module_text(out: &mut [u8], at: usize, nodes: &[u8], text: &[u8], meta: &
             q = put_name(out, q, text, lo(nodes, c, F_NAME), hi(nodes, c, F_NAME));
             q = put_text(out, q, ";\n");
         }
-        if (((cl == C_CONST) && implicit_port(&text[(lo(nodes, c, F_NAME)) as usize..(hi(nodes, c, F_NAME)) as usize])) && (oc != NO_NODE)) {
+        if ((((cl == C_CONST) && implicit_port(&text[(lo(nodes, c, F_NAME)) as usize..(hi(nodes, c, F_NAME)) as usize])) && (oc != NO_NODE)) && !(folded_tie(nodes, text, meta, ptext, c))) {
             q = put_text(out, q, "    wire ");
             q = put_name(out, q, text, lo(nodes, c, F_NAME), hi(nodes, c, F_NAME));
             q = put_text(out, q, ";\n");
@@ -2215,7 +2233,7 @@ pub fn module_text(out: &mut [u8], at: usize, nodes: &[u8], text: &[u8], meta: &
             q = (r2 as _);
             q = put_text(out, q, ";\n");
         }
-        if (((cl1 == C_CONST) && implicit_port(&text[(lo(nodes, c1, F_NAME)) as usize..(hi(nodes, c1, F_NAME)) as usize])) && (oc != NO_NODE)) {
+        if ((((cl1 == C_CONST) && implicit_port(&text[(lo(nodes, c1, F_NAME)) as usize..(hi(nodes, c1, F_NAME)) as usize])) && (oc != NO_NODE)) && !(folded_tie(nodes, text, meta, ptext, c1))) {
             q = put_text(out, q, "    assign ");
             q = put_name(out, q, text, lo(nodes, c1, F_NAME), hi(nodes, c1, F_NAME));
             q = put_text(out, q, " = ");
@@ -2276,29 +2294,49 @@ pub fn clocked(out: &mut [u8], at: usize, nodes: &[u8], text: &[u8], meta: &[u8]
         return r1;
     }
     q = (r1 as _);
-    q = put_text(out, q, "    always @(posedge clk or negedge rst_n) begin\n        if (!rst_n) begin\n");
-    let mut c: usize = 1;
-    while (c < end(nodes, 0)) {
-        if ((item_class(nodes, text, meta, ptext, c) == C_VAR) && !(ident_is(nodes, text, (c + 1), b"undefined"))) {
-            let t: i64 = sym_type(nodes, text, meta, ptext, 0, sym_of(SYM_TOP, c), 0);
-            q = put_text(out, q, "            ");
-            q = put_name(out, q, text, lo(nodes, c, F_NAME), hi(nodes, c, F_NAME));
-            q = put_text(out, q, " <= ");
-            q = put_lit(out, q, fold_val(nodes, text, meta, ptext, 0, (c + 1), 0), t);
-            q = put_text(out, q, ";\n");
+    let rf: bool = tied_on(nodes, text, meta, ptext, "rst_n");
+    let ef: bool = tied_on(nodes, text, meta, ptext, "en");
+    let mut ind: usize = 12;
+    if rf {
+        q = put_text(out, q, "    always @(posedge clk) begin\n");
+        if ef {
+            ind = 8;
+        } else {
+            q = put_text(out, q, "        if (en) begin\n");
+        }
+    } else {
+        q = put_text(out, q, "    always @(posedge clk or negedge rst_n) begin\n        if (!rst_n) begin\n");
+        let mut c: usize = 1;
+        while (c < end(nodes, 0)) {
+            if ((item_class(nodes, text, meta, ptext, c) == C_VAR) && !(ident_is(nodes, text, (c + 1), b"undefined"))) {
+                let t: i64 = sym_type(nodes, text, meta, ptext, 0, sym_of(SYM_TOP, c), 0);
+                q = put_text(out, q, "            ");
+                q = put_name(out, q, text, lo(nodes, c, F_NAME), hi(nodes, c, F_NAME));
+                q = put_text(out, q, " <= ");
+                q = put_lit(out, q, fold_val(nodes, text, meta, ptext, 0, (c + 1), 0), t);
+                q = put_text(out, q, ";\n");
+            }
+            c = end(nodes, c);
+        }
+        if ef {
+            q = put_text(out, q, "        end else begin\n");
+        } else {
+            q = put_text(out, q, "        end else if (en) begin\n");
         }
-        c = end(nodes, c);
     }
-    q = put_text(out, q, "        end else if (en) begin\n");
     if gd {
-        q = put_text(out, q, "            t27_oc_done = 1'b0;\n");
+        q = put_ind(out, q, ind);
+        q = put_text(out, q, "t27_oc_done = 1'b0;\n");
     }
-    let r2: i64 = stmts(out, q, nodes, text, meta, ptext, work, oc, M_CLOCK, oc, (oc + 1), 12, 0, gd);
+    let r2: i64 = stmts(out, q, nodes, text, meta, ptext, work, oc, M_CLOCK, oc, (oc + 1), ind, 0, gd);
     if (r2 < 0) {
         return r2;
     }
     q = (r2 as _);
-    q = put_text(out, q, "        end\n    end\n");
+    if (ind == 12) {
+        q = put_text(out, q, "        end\n");
+    }
+    q = put_text(out, q, "    end\n");
     let rc: i64 = (q as _);
     return rc;
 }
@@ -2525,6 +2563,44 @@ pub fn holds(out: &[u8], n: usize, w: &'static str) -> bool {
     return false;
 }
 
+pub fn tied_counter(nb: &mut [u8], mb: &mut [u8], rv_in: bool, rv_lo: usize, rv_hi: usize, ev_lo: usize, ev_hi: usize) -> () {
+    tnode(nb, 0, K_MODULE, 13, 0, 1);
+    tnode(nb, 1, K_CONST_DECL, 3, 1, 2);
+    vset(nb, 1, F_TYPE, 2, 4);
+    tnode(nb, 2, K_EXPR_LITERAL, 3, 0, 0);
+    vset(nb, 2, F_VALUE, 4, 5);
+    tnode(nb, 3, K_CONST_DECL, 5, 15, 20);
+    vset(nb, 3, F_TYPE, 20, 24);
+    if rv_in {
+        tnode(nb, 4, K_EXPR_IDENTIFIER, 5, rv_lo, rv_hi);
+    } else {
+        tnode(nb, 4, K_EXPR_LITERAL, 5, 0, 0);
+        vset(nb, 4, F_VALUE, rv_lo, rv_hi);
+    }
+    tnode(nb, 5, K_CONST_DECL, 7, 28, 30);
+    vset(nb, 5, F_TYPE, 20, 24);
+    tnode(nb, 6, K_EXPR_LITERAL, 7, 0, 0);
+    vset(nb, 6, F_VALUE, ev_lo, ev_hi);
+    tnode(nb, 7, K_FN_DECL, 13, 7, 15);
+    tnode(nb, 8, K_STMT_ASSIGN, 13, 0, 0);
+    tnode(nb, 9, K_EXPR_IDENTIFIER, 10, 1, 2);
+    tnode(nb, 10, K_EXPR_BINARY, 13, 0, 0);
+    vset(nb, 10, F_OP, 6, 7);
+    tnode(nb, 11, K_EXPR_IDENTIFIER, 12, 1, 2);
+    tnode(nb, 12, K_EXPR_LITERAL, 13, 0, 0);
+    vset(nb, 12, F_VALUE, 5, 6);
+    let mut i: usize = 0;
+    while (i < 13) {
+        tmeta(mb, i, 0, 0);
+        i = (i + 1);
+    }
+    tmeta(mb, 1, FLAG_MUT, 2);
+    tmeta(mb, 3, 0, 3);
+    tmeta(mb, 5, 0, 4);
+    tmeta(mb, 7, 0, 5);
+    tmeta(mb, 8, 0, 5);
+}
+
 pub const B_DOT: u8 = 46;
 
 pub const FIELDS: usize = 8;
@@ -3459,6 +3535,10 @@ pub fn steps_up(nodes: &[u8], text: &[u8], s: usize, va: usize, vb: usize) -> i6
     return cc;
 }
 
+pub fn tie_folds(s: &[u8], v: u64) -> bool {
+    return ((same(s, "rst_n") || same(s, "en")) && (v != 0));
+}
+
 pub fn trip_bound(op: &[u8], kok: bool, k: u64, sok: bool, step: u64) -> i64 {
     if (((!(kok) || !(sok)) || (step == 0)) || (k > 4611686018427387904)) {
         return NO_BOUND;

gen/rust/tri/t27b/verilog_plan.rs

@@ -601,6 +601,10 @@ pub fn implicit_port(s: &[u8]) -> bool {
     return ((same(s, "clk") || same(s, "rst_n")) || same(s, "en"));
 }
 
+pub fn tie_folds(s: &[u8], v: u64) -> bool {
+    return ((same(s, "rst_n") || same(s, "en")) && (v != 0));
+}
+
 pub const ROLE_BAD: u8 = 0;
 
 pub const ROLE_PORT: u8 = 1;