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fix(t27b): fold a constant rst_n/en tie-off out of the clocked process (Closes #10046) - #10057
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Closes #10046) A module that ties the implicit rst_n or en to true (`const rst_n : bool = true;`) was written as `wire rst_n; assign rst_n = 1'b1;` and the always block still read it (`or negedge rst_n`, `if (!rst_n)`, `else if (en)`). A test bench that writes every handle at start-up (cocotb dut_init) deposits 0 on that net, the constant driver never fires again, and the design sits in reset: CVDP moving_average_0001 failed G1 for that reason alone. verilog_plan.t27 records the rule (tie_folds): a tie of rst_n or en to true is folded out; a tie to false and a constant clk stay a wire the process reads. verilog_emit.t27 writes `always @(posedge clk)` without the reset branch when rst_n is tied on, drops `if (en)` when en is tied on, and writes no net for a folded tie (every other read of a constant is already a literal). Registers keep their reset values from `initial`. Tests: a_constant_rst_n_and_en_are_folded_out_of_the_always_block, and the negative control an_rst_n_port_keeps_its_async_reset_and_a_false_en_keeps_its_wire. gen/rust regenerated with t27c gen-rust; VerilogEmit, VerilogPlan and AstShape (verilog_plan is in its closure) resealed. All on the Railway lab. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Conflicts were in derived files only: the seals of verilog_emit/verilog_plan and gen/rust/tri/t27b/verilog_emit.rs. The specs merged cleanly (master's gHashTag#10057 rst_n/en tie-off fold and this branch's pin declarations). The derived files are recomputed from them with this tree's t27c: gen-rust for both, and both seals re-saved. Checks with this tree: seals of verilog_emit, verilog_plan, eth_top_ax7203 and xc7_primitives verify; t27c test-report and t27b test 8/8, 15/15, 2/2, 2/2. t27b verilog writes eth_top_ax7203 with all 22 pin attributes, and its synthesizable part equals the top of the bitstream tested on the board (only the test bench differs).
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Closes #10046
What
When a clocked module ties the implicit
rst_norentotrue,t27b verilognow leaves them out of the clocked process:rst_ntied on:always @(posedge clk), with noor negedge rst_nand noif (!rst_n)reset branch;entied on: noelse if (en);wire/assignfor a folded tie, since every other read of a constant is already a literal;initial.A tie to
false(held in reset / never enabled) and a constantclkstay a wire the process reads.The rule is
tie_foldsinspecs/tri/t27b/verilog_plan.t27. The writer isfolded_tie/tied_onplus the three shapes ofclocked()inspecs/tri/t27b/verilog_emit.t27. Only.t27is hand-written.Why
A cocotb harness writes 0 to every handle at start-up. That deposited 0 on the tied net, its constant driver never fired again, and the design sat in reset. That alone is why arm B failed G1 on CVDP
moving_average_0001in the Build-A-Chip-Bench proxy run.Files
specs/tri/t27b/verilog_plan.t27: rule text,tie_folds, test asserts.specs/tri/t27b/verilog_emit.t27: the fold,tied_counterfixture, 2 new tests.gen/rust/tri/t27b/verilog_{emit,plan}.rs: output oft27c gen-rust. Before regenerating, gen-rust on the pristine specs reproduced the committed files byte for byte..trinity/seals/t27b_T27b{VerilogEmit,VerilogPlan,AstShape}.json:t27c seal --save. AstShape has verilog_plan in its closure; its own gen/rust is unchanged.Lab receipts (Railway fs-lab, lane at f787afb + this diff, zig 0.16.0)
Spec tests (
t27c test-report)Mutants, to show the tests are not vacuous
folded_tiereturns false (the old behavior):a_constant_rst_n_and_en_are_folded_out_of_the_always_blockFAILS, 6/7.tie_foldsignores the value (a false tie is folded too): both new tests FAIL, 5/7. That includes the negative controlan_rst_n_port_keeps_its_async_reset_and_a_false_en_keeps_its_wire.moving_average_0001, arm B, same .t27 (sha256 4642aec5...), re-emitted with the rebuilt t27b and run through the same gate driver:
The spec's own emitted test bench (Icarus,
-DT27B_TESTBENCH) passes: 4 tests, 0 failed. The diff of the emitted .v contains the fold and nothing else.Controls: old vs new t27b on every other spec it is pointed at
verilog_lib,verilog_use,verilog_widthsqueen/actors_hw_jtag(rst_n/enare= undefinedinput ports)verilog_prim(ties true)equiv_make/equiv_inductproves old == new (40$equivcells)queen/actors_hw_top(ties true)$equivcells)A mutant of actors_hw_top (
div + 2) is rejected by the same equivalence check: 8 cells unproven.Wider checks
t27c suite --repo-root .: exits 1, but its per-phase summary is identical to the pristine f787afb tree. None of the touched or affected specs appear in its failures.🤖 Generated with Claude Code