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fpga(ax7203): rc_filter PLL params back to f64 so t27b passes the spec again (Closes #10313) - #10314
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…c again (Closes #10313) master's t27b-native-ratchet reads `specs/fpga/rc_filter_ax7203.t27: ledger pass, now blocked: type comptime_float`. #10278 ledgered the spec as t27b pass; #10296 then typed PLLE2_ADV's CLKIN1_PERIOD and REF_JITTER1 as comptime_float so t27c gen-verilog would not emit `input real`, and t27b rejects a comptime_float parameter. #10302 made gen-verilog skip t27b bitstream specs, so that reason is gone: the two parameters go back to f64 and the doc comment says why. Measured on the Railway lab at master 9da2c5f, t27b and t27c built there: - t27b on master's spec: "unsupported construct type comptime_float at line 247"; on this spec: accepted, and `t27b build --elf` writes the object (the x86 lab has no t27b JIT; CI's arm64 runs the tests). - `t27b verilog`: same 608 lines as master's; only the five `// ... (line N)` comments move by 2. The PLL instance still reads CLKIN1_PERIOD(5.0), REF_JITTER1(0.01), so the board RTL does not change. - reference (t27c test-report, zig 0.16.0): 10 of 10 pass, 0 vacuous. - seal regenerated with `t27c seal --save`: spec_hash 8fba8a41. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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October 18, 2026 08:28
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Closes #10313
t27b-native-ratcheton master listsspecs/fpga/rc_filter_ax7203.t27as UNEXPECTED FAILURE:ledger pass, now blocked: type comptime_float.PLLE2_ADV'sCLKIN1_PERIODandREF_JITTER1ascomptime_float, so that t27c gen-verilog would not emitinput real.comptime_floatparameter.This PR puts the two parameters back to
f64and adds a two-line doc comment saying why.Measured (Railway lab, master 9da2c5f, t27b and t27c built there)
unsupported construct type comptime_float at line 247t27b build --elfwrites the objectt27b verilog// (line N)comments shifted by 2; the PLL instance keepsCLKIN1_PERIOD(5.0), REF_JITTER1(0.01)The lab is x86_64, which has no t27b JIT, so the t27b test verdict itself comes from CI's arm64
t27b-native-ratcheton this PR.The seal was regenerated with
t27c seal --save(spec_hash8fba8a41); the tests in the seal are still 10 of 10.Not in scope
specs/fpga/ddr3_head_bandwidth.t27, the ratchet's other UNEXPECTED FAILURE (ExprIdentifier(undeclared)), and the 12 UNLISTED rows.🤖 Generated with Claude Code