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fpga(ax7203): ddr3_head_bandwidth lowers under t27b again -- its state-reading pins become registers (Closes #10327) - #10328
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…e-reading pins become registers (Closes #10327) master's t27b-native-ratchet reads `specs/fpga/ddr3_head_bandwidth.t27: ledger pass, now blocked: ExprIdentifier(undeclared)`. The module-level nets uart_tx, led_2 and led_3 read vars (st, verdict, hb), which t27b's test path cannot do. As in rc_filter (#10278) they become pub var registers set at the top of on_clock; on_clock takes the core's UART output as core_uart_tx. The pinout, core instance, traffic, checksum, divider and receipt are unchanged. Measured on the Railway lab at master 7912660: - t27b on master's spec: unsupported construct ExprIdentifier(undeclared) for st, verdict, hb; on this spec: no blocker (x86 stops at the JIT message, CI's arm64 runs the tests). - t27b verilog: the module differs from master's only in uart_tx, led_2 and led_3 (output reg, assigned in the clocked process). - reference (t27c test-report, zig 0.16.0): 12 of 12 pass, 0 vacuous. - seal regenerated with `t27c seal --save`: spec_hash 59242e4b. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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Closes #10327
master's
t27b-native-ratchetis red onspecs/fpga/ddr3_head_bandwidth.t27: ledger pass, now blocked: ExprIdentifier(undeclared)(run 39105096338), so every PR that merges master inherits the red check, #10278 among them.Cause
The nets
uart_tx,led_2andled_3read the varsst,tx_sh,verdictandhb. t27b's test path cannot read a var from a net; it reports the three names and blames the line of the first fn. Same shape as rc_filter in #10278.Change
uart_tx,led_2,led_3arepub varregisters set at the top ofon_clockfrom the state at the clock.led_0andled_1only mirror the core and stay nets.on_clocktakes the core's UART output ascore_uart_tx(t27b binds a parameter named<instance>_<output>to that instance's output). The 32 calls in the spec's tests pass it.t27c seal --saveon the lab.Unchanged: the pinout, the LiteDRAM instance, the write and read traffic, the checksum, the divider and the receipt. The ledger row stays
passandmax_not_passis untouched.Measured on the Railway lab (master 7912660)
t27b test --blockerson master's spec:unknown name st,verdict,hb. On this spec: no blocker; x86 stops at "the t27b JIT runs only on arm64", after lowering. CI's arm64 runs the tests.t27b verilog: 908 lines on master, 914 here. The only differences areuart_tx,led_2,led_3asoutput reg, with the reset values and the clocked assignments.t27c test-report, zig 0.16.0): 12 of 12 pass, 0 vacuous.59242e4b, tests 12/12.Note for the board
The three pins now come one flop after the state, and the UART pin also idles high while the core is in reset. The 115200 baud receipt (868 clocks per bit) and the LEDs are not affected by one clock. The bitstream behind the 2769 MB/s measurement was built from the earlier netlist; a rebuild is not part of this change.
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