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fpga(ax7203): ddr3_head_bandwidth lowers under t27b again -- its state-reading pins become registers (Closes #10327) #10328

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Merged
gHashTag merged 1 commit into from
Oct 18, 2026
Merged

fpga(ax7203): ddr3_head_bandwidth lowers under t27b again -- its state-reading pins become registers (Closes #10327) #10328

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18 changes: 9 additions & 9 deletions .trinity/seals/fpga_FpgaDdr3HeadBandwidth.json
View file
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Original file line number Diff line number Diff line change
@@ -1,24 +1,24 @@
{
"built_by": "t27c-bootstrap@0.5.2+a86b691b1",
"built_by": "t27c-bootstrap@0.5.2+79126608b",
"closure": [],
"config": "gen=c,rust,verilog,zig;tests=zig",
"gen_hash_c": "sha256:5e5da515c467d127f3230cea988388245fcf1ae9daa81d01eb3b76b41911eb5d",
"gen_hash_rust": "sha256:62ef58250c31f22195fca1be94e6ea51b3c2878ba65456b736137437db34a458",
"gen_hash_verilog": "sha256:406c22b582d5a8e113cc3948c2cfc8ad4fdd283b5a136b5bd41df38790b251e7",
"gen_hash_zig": "sha256:825465e68cc9f1a59c3d588fdb208a040f312f03ea4e125672a2c3466173a75f",
"gen_hash_c": "sha256:23ce13530186a4f63ca3f42565c4f3b5ef346c5f4a8d8ba2e8ba1f5fe0a6de0e",
"gen_hash_rust": "sha256:d61c73f5c49d32d0d11aeafd20abb948f6ab4e0fcab4bafe48f005f7c2f5d8de",
"gen_hash_verilog": "sha256:65e8b6194fd2f634281e7c493a3bcf609afdc8850c049c4e0c6da69c989750a1",
"gen_hash_zig": "sha256:d7b5263c8fdf4d0ca62310bffd53858e33fb44556eda898c929be756b53c9c66",
"module": "FpgaDdr3HeadBandwidth",
"ring": 12,
"seal_schema": 2,
"sealed_at": "2026-10-18T05:05:36Z",
"sealed_at": "2026-10-18T09:08:23Z",
"sealed_by": "t27c-bootstrap@0.5.2",
"spec_hash": "sha256:5ae8e395f6f3be001f54052ae71d11f6093802ed9bad6ccbd32358234edaed6a",
"spec_hash": "sha256:59242e4bc9430d41386640efe931ac3996a02afcee1b5142451750a48d99fc89",
"spec_path": "specs/fpga/ddr3_head_bandwidth.t27",
"tests": {
"failed": 0,
"failing": [],
"forced": false,
"passed": 11,
"total": 11,
"passed": 12,
"total": 12,
"vacuous": 0
},
"toolchain": {
Expand Down
104 changes: 68 additions & 36 deletions specs/fpga/ddr3_head_bandwidth.t27
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Original file line number Diff line number Diff line change
Expand Up @@ -255,7 +255,10 @@ const rst_n : bool = !core.user_rst;
const en : bool = true;

; --- the pins out -------------------------------------------------------------------------------
pub const uart_tx : bool = (st == ST_REPORT and (tx_sh & 1) == 1) or (st != ST_REPORT and core.uart_tx);
; The three pins that read the run (the UART, D14, D15) are registers set in on_clock from the state at the
; clock (a pub var is an output reg): t27b's test path cannot read a var from a net. The two LEDs that
; only mirror the core stay nets.
pub var uart_tx : bool = true;
const uart_tx_LOC : str = "N15";
const uart_tx_IOSTANDARD : str = "LVCMOS33";
pub const led_0 : bool = !core.init_done;
Expand All @@ -264,10 +267,10 @@ const led_0_IOSTANDARD : str = "LVCMOS33";
pub const led_1 : bool = !core.init_error;
const led_1_LOC : str = "C13";
const led_1_IOSTANDARD : str = "LVCMOS33";
pub const led_2 : bool = !(st == ST_REPORT and verdict == V_PASS);
pub var led_2 : bool = true;
const led_2_LOC : str = "D14";
const led_2_IOSTANDARD : str = "LVCMOS33";
pub const led_3 : bool = ((hb >> 26) & 1) == 1;
pub var led_3 : bool = false;
const led_3_LOC : str = "D15";
const led_3_IOSTANDARD : str = "LVCMOS33";

Expand Down Expand Up @@ -637,7 +640,10 @@ pub fn field(s: u8, n: u32, w: u32, r: u32, m: u32, ws: u64, rs: u64, e: u32, l:
}

// Every var is read before it is written, so the test's order and the clock edge agree.
fn on_clock(core_init_done: bool, core_init_error: bool, core_user_port_native_0_cmd_ready: bool, core_user_port_native_0_wdata_ready: bool, core_user_port_native_0_rdata_valid: bool, core_user_port_native_0_rdata_data__0: u64, core_user_port_native_0_rdata_data__1: u64, core_user_port_native_0_rdata_data__2: u64, core_user_port_native_0_rdata_data__3: u64) {
fn on_clock(core_init_done: bool, core_init_error: bool, core_user_port_native_0_cmd_ready: bool, core_user_port_native_0_wdata_ready: bool, core_user_port_native_0_rdata_valid: bool, core_user_port_native_0_rdata_data__0: u64, core_user_port_native_0_rdata_data__1: u64, core_user_port_native_0_rdata_data__2: u64, core_user_port_native_0_rdata_data__3: u64, core_uart_tx: bool) {
uart_tx = (st == ST_REPORT and (tx_sh & 1) == 1) or (st != ST_REPORT and core_uart_tx);
led_2 = !(st == ST_REPORT and verdict == V_PASS);
led_3 = ((hb >> 26) & 1) == 1;
hb = hb +% 1;
if (st == ST_WAIT) {
if (core_init_error) {
Expand Down Expand Up @@ -835,37 +841,37 @@ test a_run_of_three_beats_reads_back_what_it_wrote {
err = 0;
dnum = 0;
rv = false;
on_clock(false, false, true, true, false, 0, 0, 0, 0);
on_clock(false, false, true, true, false, 0, 0, 0, 0, true);
assert_eq(st, ST_WAIT);
on_clock(true, false, true, true, false, 0, 0, 0, 0);
on_clock(true, false, true, true, false, 0, 0, 0, 0, true);
assert_eq(st, ST_WRITE);
on_clock(true, false, true, false, false, 0, 0, 0, 0);
on_clock(true, false, true, false, false, 0, 0, 0, 0, true);
assert_eq(ci, 1);
assert_eq(di, 0);
on_clock(true, false, true, true, false, 0, 0, 0, 0);
on_clock(true, false, true, true, false, 0, 0, 0, 0);
on_clock(true, false, false, true, false, 0, 0, 0, 0);
on_clock(true, false, true, true, false, 0, 0, 0, 0, true);
on_clock(true, false, true, true, false, 0, 0, 0, 0, true);
on_clock(true, false, false, true, false, 0, 0, 0, 0, true);
assert_eq(ci, 3);
assert_eq(di, 3);
assert_eq(wcyc, 4);
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
assert_eq(st, ST_READ);
assert_eq(ci, 0);
on_clock(true, false, true, false, true, lane_word(0, 0), lane_word(0, 1), lane_word(0, 2), lane_word(0, 3));
on_clock(true, false, true, false, true, lane_word(0, 0), lane_word(0, 1), lane_word(0, 2), lane_word(0, 3), true);
assert_eq(ri, 0);
on_clock(true, false, true, false, true, lane_word(1, 0), lane_word(1, 1), lane_word(1, 2), lane_word(1, 3));
on_clock(true, false, true, false, true, lane_word(1, 0), lane_word(1, 1), lane_word(1, 2), lane_word(1, 3), true);
assert_eq(ri, 1);
on_clock(true, false, true, false, true, lane_word(2, 0), lane_word(2, 1), lane_word(2, 2), lane_word(2, 3));
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, true, false, true, lane_word(2, 0), lane_word(2, 1), lane_word(2, 2), lane_word(2, 3), true);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
assert_eq(ci, 3);
assert_eq(ri, 3);
assert_eq(rcyc, 4);
assert_eq(dnum, 3 * BEAT_X_MHZ);
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
assert_eq(st, ST_DIV);
var k : u8 = 0;
while (k < 33) {
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
k = k + 1;
}
assert_eq(st, ST_REPORT);
Expand All @@ -886,14 +892,14 @@ test a_beat_read_back_wrong_is_a_fail_at_any_rate {
dnum = 0;
rv = false;
wsum = fold(fold(0, lane_word(0, 0), lane_word(0, 1), lane_word(0, 2), lane_word(0, 3)), lane_word(1, 0), lane_word(1, 1), lane_word(1, 2), lane_word(1, 3));
on_clock(true, false, false, false, true, lane_word(0, 0), lane_word(0, 1), lane_word(0, 2), lane_word(0, 3));
on_clock(true, false, false, false, true, lane_word(1, 0), lane_word(1, 1), lane_word(1, 2) ^ 4, lane_word(1, 3));
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, false, false, true, lane_word(0, 0), lane_word(0, 1), lane_word(0, 2), lane_word(0, 3), true);
on_clock(true, false, false, false, true, lane_word(1, 0), lane_word(1, 1), lane_word(1, 2) ^ 4, lane_word(1, 3), true);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
assert_eq(rcyc, 3);
var k : u8 = 0;
while (k < 33) {
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
k = k + 1;
}
assert_eq(st, ST_REPORT);
Expand All @@ -912,15 +918,15 @@ test a_slow_read_is_slow_and_a_slower_one_killed {
err = 0;
dnum = 0;
rv = false;
on_clock(true, false, false, false, true, lane_word(0, 0), lane_word(0, 1), lane_word(0, 2), lane_word(0, 3));
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, false, false, true, lane_word(1, 0), lane_word(1, 1), lane_word(1, 2), lane_word(1, 3));
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, false, false, true, lane_word(2, 0), lane_word(2, 1), lane_word(2, 2), lane_word(2, 3));
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, false, false, true, lane_word(0, 0), lane_word(0, 1), lane_word(0, 2), lane_word(0, 3), true);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
on_clock(true, false, false, false, true, lane_word(1, 0), lane_word(1, 1), lane_word(1, 2), lane_word(1, 3), true);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
on_clock(true, false, false, false, true, lane_word(2, 0), lane_word(2, 1), lane_word(2, 2), lane_word(2, 3), true);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
var k : u8 = 0;
while (k < 34) {
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
k = k + 1;
}
assert_eq(rcyc, 6);
Expand All @@ -931,13 +937,13 @@ test a_slow_read_is_slow_and_a_slower_one_killed {
rcyc = 3;
dnum = 0;
rv = false;
on_clock(true, false, false, false, true, lane_word(0, 0), lane_word(0, 1), lane_word(0, 2), lane_word(0, 3));
on_clock(true, false, false, false, true, lane_word(1, 0), lane_word(1, 1), lane_word(1, 2), lane_word(1, 3));
on_clock(true, false, false, false, true, lane_word(2, 0), lane_word(2, 1), lane_word(2, 2), lane_word(2, 3));
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, false, false, true, lane_word(0, 0), lane_word(0, 1), lane_word(0, 2), lane_word(0, 3), true);
on_clock(true, false, false, false, true, lane_word(1, 0), lane_word(1, 1), lane_word(1, 2), lane_word(1, 3), true);
on_clock(true, false, false, false, true, lane_word(2, 0), lane_word(2, 1), lane_word(2, 2), lane_word(2, 3), true);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
k = 0;
while (k < 34) {
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
k = k + 1;
}
assert_eq(rcyc, 7);
Expand All @@ -948,7 +954,7 @@ test a_slow_read_is_slow_and_a_slower_one_killed {
test a_failed_calibration_reports_fail {
st = ST_WAIT;
verdict = V_PASS;
on_clock(false, true, false, false, false, 0, 0, 0, 0);
on_clock(false, true, false, false, false, 0, 0, 0, 0, true);
assert_eq(st, ST_REPORT);
assert_eq(verdict, V_FAIL);
}
Expand All @@ -975,7 +981,7 @@ test the_receipt_line_says_what_was_measured {
var ch : u8 = 0;
var line : u32 = 0;
while (line < 2) {
on_clock(true, false, false, false, false, 0, 0, 0, 0);
on_clock(true, false, false, false, false, 0, 0, 0, 0, true);
bits = bits + 1;
if (tx_left == 9) {
assert_eq(tx_sh & 1, 0);
Expand Down Expand Up @@ -1013,3 +1019,29 @@ test the_receipt_line_says_what_was_measured {
assert_eq(lines, 2);
assert_eq(bits, (2 * 167 - 1) * 10 + 1);
}

test the_pins_that_read_the_run_are_set_from_its_state {
baud_div = 868;
tx_cnt = 0;
tx_left = 0;
st = ST_WAIT;
verdict = V_PASS;
hb = 0;
tx_sh = 1023;
on_clock(false, false, false, false, false, 0, 0, 0, 0, false);
assert_eq(uart_tx, false);
assert_eq(led_2, true);
assert_eq(led_3, false);
on_clock(false, false, false, false, false, 0, 0, 0, 0, true);
assert_eq(uart_tx, true);
st = ST_REPORT;
tx_sh = 1022;
hb = 67108864;
on_clock(false, false, false, false, false, 0, 0, 0, 0, true);
assert_eq(uart_tx, false);
assert_eq(led_2, false);
assert_eq(led_3, true);
tx_sh = 1023;
on_clock(false, false, false, false, false, 0, 0, 0, 0, false);
assert_eq(uart_tx, true);
}
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