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skills: tri-pipeline lists only commands that exist; analog-emulation gets the toolchain map and the loop tick protocol (Closes #10499) - #10500
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… gets the toolchain map and the loop tick protocol (Closes #10499) tri-pipeline named `tri verify` (does not exist), `tri experience query` (only `save` exists) and said `tri test` runs one spec (scripts/tri test is the whole-repo suite). Rewritten from `--help` of target/release/tri and t27c 0.5.2 on 2026-10-18; the root-level tri-pipeline.md becomes a pointer so there is one list. analog-emulation: delta-form step and proved stability, unsigned in hardware (t27b verilog refuses signed types), the SPICE reader as a t27o front end, a toolchain table, and the six-step overnight loop tick (state, anomalies, Opus review / Sonnet lanes, merge green, write state, reports only on the owner's yes). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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… mentions (Closes #10513) (#10514) #10500 removed `tri verify` and `tri experience query` from .claude/skills/tri-pipeline.md, so the equality ratchet read 138 against the ceiling 140 and "Documented t27c subcommands exist" failed on master and on every PR after it. One constant inside a gate tool already listed in tools/policy/foreign-exceptions.txt (the PR #9277 pattern). `python3 tools/check_documented_commands_exist.py` now prints "ok". Co-authored-by: Claude <claude@anthropic.com> Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
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Closes #10499
tri-pipeline
Rewritten from
--helpoftarget/release/triandt27c0.5.2 (2026-10-18). Removed:tri verify(exists nowhere),tri experience query(onlysaveexists). Corrected:scripts/tri testis the whole-repot27c suite; the one-spec runner istarget/release/tri test <spec>;t27c test <spec>only lists tests. Added:t27b verilog(refuses signed types),tri t27o,tri topic,tri loop claim,tri pr ready|landed,tri seals,tri hooks, the MCP servers and what each really checks. The root-leveltri-pipeline.mdbecomes a pointer, so there is one list.Commands named, each seen in a
--helpoutput on this date: t27c check, test-report, test, seal (--save, --verify), gen-verilog, gen-c, gen-rust, gen, fpga-build, fpga-flash; tri test, gen, t27o, topic, loop claim, pr ready, pr landed, night, red, ci, gates, merging, lanes, seals, hooks, experience save, loop-help (scripts/tri); t27b verilog, test (cli/t27b/src/main.rs usage).analog-emulation
Delta-form step and proved stability (from #10487's design), unsigned arithmetic in hardware, the SPICE reader as a t27o front end (one converter, DRY), a toolchain table, and the six-step overnight loop tick: read the ledger, look for anomalies first, Opus review / Sonnet lanes, merge only green, write state, partner reports only on the owner's yes.
Related defects filed from the same survey: #10497 (
tri testignores vacuous passes), #10498 (no ax7203 in fpga-build / fpga-flash).🤖 Generated with Claude Code