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analog: linear.t27 -- linear state-space cell, MNA folded to x' = x + rnd(Dx + Nu), reproduces M0 bit for bit (Closes #10487) - #10511
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… rnd(Dx + Nu), reproduces M0 bit for bit (Closes #10487) M1 of #10486. specs/analog/linear.t27 is a linear analog cell for small R / C / L circuits with one voltage source and a fixed step. Modified nodal analysis with backward Euler is folded at compile time to D = M - I and N, stored as Q.24 integers, and one step is x_i' = x_i + rnd(sum_j D_ij x_j + N_i u) with one rounding per state, half away from zero. The step is unsigned only (the fns a board top reaches take bool and u32/u64): states, constants and inputs are sign-magnitude u32 words with bit 31 as the direction flag; the positive and the negative products add into two u64 registers, one subtraction and one rounding give the delta. No signed type, because `t27b verilog` refuses one. Circuits as element tables: the M0 RC (R=1k, C=1n, dt=50ns), a series RLC (R=100, L=10uH, C=1nF, dt=5ns, inductor current stored times 100 Ohm), a 3-node and a 5-node RC ladder. The tests derive every stored constant: they stamp A, C/dt and B from the element table, solve by Gauss-Jordan elimination with partial pivoting in f64, and assert each integer equals round(value * 2^24). Mis-stamped elements (a conductance, a capacitor, an inductor on the wrong node) change a derived value and fail; t27c seal refuses the mutant. Stability is ||M_q^256||_inf < 1 per circuit, with unstable matrices failing the same check. The RC circuit gives M0's A, B and S = 0x77EDFF0295C3FE9E. Error against the f64 backward Euler run of the same method is bounded per circuit (3, 9, 10, 41 LSB). No board tops and no Verilog here; those are M1b (#10496). Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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Closes #10487
M1 of #10486.
specs/analog/linear.t27is a linear analog cell for small R / C / L circuits with one voltage source and a fixed step. M0 (specs/fpga/rc_filter_ax7203.t27) is its 1x1 case and is reproduced bit for bit.What it is
D = M - IandN, stored as Q.24 integers. One step isx_i' = x_i + rnd(sum_j D_ij x_j + N_i u): exact wide sum, one rounding per state, half away from zero.u32words (bit 31 = direction flag); positive and negative products add into twou64registers (pos_after,neg_after);delta_ofdoes the one subtraction and the one rounding. Noi32/i64anywhere, becauset27b verilogrefuses signed types. The fns fromvin_attofoldtake only bool and unsigned words, so the board tops of M1b can reach them.A,C/dt,Bfrom the table, solve by Gauss-Jordan elimination with partial pivoting in f64, and assert each integer equalsround(value * 2^24). No derived value is within 1e-4 of a rounding tie;|A X - R| < 1e-12.Measured (all from
t27c test-report/t27c sealon this branch)tri test specs/analog/linear.t27: 14 pass, 0 fail.0x77EDFF0295C3FE9E. M0's numbers are pinned as literals in the test (useof M0 would carry its on_clock/PLL top into every importer).||M_q^256||_inf < 1: RC 3.8e-6, RLC 2.7e-3, ladder-3 0.098, ladder-5 0.445. The RLC has||M_q||_inf = 1.045 > 1and is still stable, which is why the plain norm is not used. Failing on purpose: sign of D flipped (M = 1 + 1/21), M = I, and a coupled pair with eigenvalue 1.4.LAD3_A[3]2 -> 1) fails 3 of 14 tests, andt27c seal --saveon it refuses with exit 1 ("refusing to seal ...: 3 of 14 test(s) FAIL"). Changing one stored constant by 1 (LAD3_D[1], 696219 -> 696218) fails the same 3 of 14 tests undertest-report.t27c seal specs/analog/linear.t27 --save, then--verify: spec, zig, verilog, c, rust hashes all MATCH. Seal committed as.trinity/seals/analog_AnalogLinear.json.tri types dupandtri types redef: nothing new.Not covered (stated in the spec header)
No board tops, bitstream, LUT/FF/DSP/Fmax or UART receipt (M1b, #10496). No netlist reader (M2). No nonlinear device (M3). Nothing about the continuous circuit, only backward Euler at this dt. Nothing about power. A capacitor or inductor on the driven node is refused by
table_ok.docs/reports/t27b_expectations.jsonis not edited; the steward adds the ledger row.Notes for review
vin_at,round_backandfoldare byte-identical to M0's (t27c dupes --bodies). They cannot come from auseof M0 (see above). A follow-up can make M0usethem from this file: t27b carries only the fns the hardware reaches, so no f64 code would reach the board.fabs64joins three other private abs helpers in the corpus; none ispuband shareable.pub const X : [1]u32 = [798915];, lowers to the Zig array TYPE[798915]and the spec fails to compile;[a | 0]and[798915] ** 1lower correctly, and so does the same literal in a function body. Worked around with** 1.t27bwas not built in this sandbox, sot27b verilogwas not run on the scalar step; the step uses only bool,u32andu64.🤖 Generated with Claude Code