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analog: sar_cdac.t27 -- the SAR ADC split capacitive DAC with its 1-unit bridge, charge redistribution against ngspice (Closes #10540) #10575

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Merged
gHashTag merged 1 commit into from
Oct 18, 2026
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analog: sar_cdac.t27 -- the SAR ADC split capacitive DAC with its 1-unit bridge, charge redistribution against ngspice (Closes #10540) #10575

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33 changes: 33 additions & 0 deletions .trinity/seals/analog_AnalogSarCdac.json
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{
"built_by": "t27c-bootstrap@0.5.2+9b556b7c3",
"closure": [
{
"spec": "specs/analog/linear.t27",
"spec_hash": "sha256:3ddef7be183aba583ed285334ee389b48a65b41335e98914514235db7c4e5d62"
}
],
"config": "gen=c,rust,verilog,zig;tests=zig",
"gen_hash_c": "sha256:a4fb3d480089e4e90b488d2470ac9e1c592434c4264457ba3be4655c1237ec9c",
"gen_hash_rust": "sha256:76e21ceaecfeac4d922f02d53f9a9a877b2404bacc43797bc1c3ccb674d919ea",
"gen_hash_verilog": "sha256:780bcc67575db05dade43bfbe1b3d37431adb427076b86b0958269568a62fcbd",
"gen_hash_zig": "sha256:511cd3ff1f9ed0df9ffc60e32b4a45a4bac154a42e6a3299b38d1dfd42bdad10",
"module": "AnalogSarCdac",
"ring": 12,
"seal_schema": 2,
"sealed_at": "2026-10-18T17:35:26Z",
"sealed_by": "t27c-bootstrap@0.5.2",
"spec_hash": "sha256:0fa41f4de9f797a091d30fdf51896c81971b6d0504587431267172179a711309",
"spec_path": "specs/analog/sar_cdac.t27",
"tests": {
"failed": 0,
"failing": [],
"forced": false,
"passed": 12,
"total": 12,
"vacuous": 0
},
"toolchain": {
"test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
"zig": "0.16.0"
}
}
159 changes: 159 additions & 0 deletions specs/analog/decks/sar_cdac_diff.cir
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SAR ADC differential split capacitive DAC, x17 (VDN) and x18 (VDP) of the golden deck, ideal capacitors, 1024 codes in one run
* specs/analog/decks/sar_cdac_diff.cir -- test data for specs/analog/sar_cdac.t27 (#10540). A plain netlist, no .control block.
* Two copies of the Diff_cap_DAC topology of sar_cdac_half.cir (see there for the unit counts and the deck lines they come from).
* P half (x18, top plate mp, net1 lp, plates pp1..pp10): sampled at 0.875 V. N half (x17, top plate mn, net1 ln, plates pn1..pn10): sampled at 0.625 V.
* Every plate rests at VCM = 0.75 V until 10 ns. Interval n (n = 0..1023, 10 ns each): P plate j is at VDD = 1.5 V when bit j-1 of n is 1 and at 0 V
* when it is 0; the N plates are the complement (neg_bottom_plate_logic: Bit_n = not Bit once the bit is decided), so the N code is 1023 - n.
* The network is algebraic (capacitors only), so the settled voltage of an interval does not depend on the time grid.
* Read the LAST printed point inside each interval. Run: ngspice -b sar_cdac_diff.cir (the spec records v(mp) and v(mn) for 16 codes;
* .print shows 7 digits, the spec's values were read with set numdgt=15 in a control block wrapped around this same netlist).
Cp1_1 lp pp1 100f IC=0.125
Cp2_1 lp pp2 100f IC=0.125
Cp2_2 lp pp2 100f IC=0.125
Cp3_1 lp pp3 100f IC=0.125
Cp3_2 lp pp3 100f IC=0.125
Cp3_3 lp pp3 100f IC=0.125
Cp3_4 lp pp3 100f IC=0.125
Cp4_1 lp pp4 100f IC=0.125
Cp4_2 lp pp4 100f IC=0.125
Cp4_3 lp pp4 100f IC=0.125
Cp4_4 lp pp4 100f IC=0.125
Cp4_5 lp pp4 100f IC=0.125
Cp4_6 lp pp4 100f IC=0.125
Cp4_7 lp pp4 100f IC=0.125
Cp4_8 lp pp4 100f IC=0.125
Cp5_1 lp pp5 100f IC=0.125
Cp5_2 lp pp5 100f IC=0.125
Cp5_3 lp pp5 100f IC=0.125
Cp5_4 lp pp5 100f IC=0.125
Cp5_5 lp pp5 100f IC=0.125
Cp5_6 lp pp5 100f IC=0.125
Cp5_7 lp pp5 100f IC=0.125
Cp5_8 lp pp5 100f IC=0.125
Cp5_9 lp pp5 100f IC=0.125
Cp5_10 lp pp5 100f IC=0.125
Cp5_11 lp pp5 100f IC=0.125
Cp5_12 lp pp5 100f IC=0.125
Cp5_13 lp pp5 100f IC=0.125
Cp5_14 lp pp5 100f IC=0.125
Cp5_15 lp pp5 100f IC=0.125
Cp5_16 lp pp5 100f IC=0.125
Cp6_1 mp pp6 100f IC=0.125
Cp7_1 mp pp7 100f IC=0.125
Cp7_2 mp pp7 100f IC=0.125
Cp8_1 mp pp8 100f IC=0.125
Cp8_2 mp pp8 100f IC=0.125
Cp8_3 mp pp8 100f IC=0.125
Cp8_4 mp pp8 100f IC=0.125
Cp9_1 mp pp9 100f IC=0.125
Cp9_2 mp pp9 100f IC=0.125
Cp9_3 mp pp9 100f IC=0.125
Cp9_4 mp pp9 100f IC=0.125
Cp9_5 mp pp9 100f IC=0.125
Cp9_6 mp pp9 100f IC=0.125
Cp9_7 mp pp9 100f IC=0.125
Cp9_8 mp pp9 100f IC=0.125
Cp10_1 mp pp10 100f IC=0.125
Cp10_2 mp pp10 100f IC=0.125
Cp10_3 mp pp10 100f IC=0.125
Cp10_4 mp pp10 100f IC=0.125
Cp10_5 mp pp10 100f IC=0.125
Cp10_6 mp pp10 100f IC=0.125
Cp10_7 mp pp10 100f IC=0.125
Cp10_8 mp pp10 100f IC=0.125
Cp10_9 mp pp10 100f IC=0.125
Cp10_10 mp pp10 100f IC=0.125
Cp10_11 mp pp10 100f IC=0.125
Cp10_12 mp pp10 100f IC=0.125
Cp10_13 mp pp10 100f IC=0.125
Cp10_14 mp pp10 100f IC=0.125
Cp10_15 mp pp10 100f IC=0.125
Cp10_16 mp pp10 100f IC=0.125
Cbrp lp mp 100f IC=0
Cn1_1 ln pn1 100f IC=-0.125
Cn2_1 ln pn2 100f IC=-0.125
Cn2_2 ln pn2 100f IC=-0.125
Cn3_1 ln pn3 100f IC=-0.125
Cn3_2 ln pn3 100f IC=-0.125
Cn3_3 ln pn3 100f IC=-0.125
Cn3_4 ln pn3 100f IC=-0.125
Cn4_1 ln pn4 100f IC=-0.125
Cn4_2 ln pn4 100f IC=-0.125
Cn4_3 ln pn4 100f IC=-0.125
Cn4_4 ln pn4 100f IC=-0.125
Cn4_5 ln pn4 100f IC=-0.125
Cn4_6 ln pn4 100f IC=-0.125
Cn4_7 ln pn4 100f IC=-0.125
Cn4_8 ln pn4 100f IC=-0.125
Cn5_1 ln pn5 100f IC=-0.125
Cn5_2 ln pn5 100f IC=-0.125
Cn5_3 ln pn5 100f IC=-0.125
Cn5_4 ln pn5 100f IC=-0.125
Cn5_5 ln pn5 100f IC=-0.125
Cn5_6 ln pn5 100f IC=-0.125
Cn5_7 ln pn5 100f IC=-0.125
Cn5_8 ln pn5 100f IC=-0.125
Cn5_9 ln pn5 100f IC=-0.125
Cn5_10 ln pn5 100f IC=-0.125
Cn5_11 ln pn5 100f IC=-0.125
Cn5_12 ln pn5 100f IC=-0.125
Cn5_13 ln pn5 100f IC=-0.125
Cn5_14 ln pn5 100f IC=-0.125
Cn5_15 ln pn5 100f IC=-0.125
Cn5_16 ln pn5 100f IC=-0.125
Cn6_1 mn pn6 100f IC=-0.125
Cn7_1 mn pn7 100f IC=-0.125
Cn7_2 mn pn7 100f IC=-0.125
Cn8_1 mn pn8 100f IC=-0.125
Cn8_2 mn pn8 100f IC=-0.125
Cn8_3 mn pn8 100f IC=-0.125
Cn8_4 mn pn8 100f IC=-0.125
Cn9_1 mn pn9 100f IC=-0.125
Cn9_2 mn pn9 100f IC=-0.125
Cn9_3 mn pn9 100f IC=-0.125
Cn9_4 mn pn9 100f IC=-0.125
Cn9_5 mn pn9 100f IC=-0.125
Cn9_6 mn pn9 100f IC=-0.125
Cn9_7 mn pn9 100f IC=-0.125
Cn9_8 mn pn9 100f IC=-0.125
Cn10_1 mn pn10 100f IC=-0.125
Cn10_2 mn pn10 100f IC=-0.125
Cn10_3 mn pn10 100f IC=-0.125
Cn10_4 mn pn10 100f IC=-0.125
Cn10_5 mn pn10 100f IC=-0.125
Cn10_6 mn pn10 100f IC=-0.125
Cn10_7 mn pn10 100f IC=-0.125
Cn10_8 mn pn10 100f IC=-0.125
Cn10_9 mn pn10 100f IC=-0.125
Cn10_10 mn pn10 100f IC=-0.125
Cn10_11 mn pn10 100f IC=-0.125
Cn10_12 mn pn10 100f IC=-0.125
Cn10_13 mn pn10 100f IC=-0.125
Cn10_14 mn pn10 100f IC=-0.125
Cn10_15 mn pn10 100f IC=-0.125
Cn10_16 mn pn10 100f IC=-0.125
Cbrn ln mn 100f IC=0
Bp1 pp1 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/1)-2*floor(floor((time-10n)/10n)/2))-1)
Bp2 pp2 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/2)-2*floor(floor((time-10n)/10n)/4))-1)
Bp3 pp3 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/4)-2*floor(floor((time-10n)/10n)/8))-1)
Bp4 pp4 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/8)-2*floor(floor((time-10n)/10n)/16))-1)
Bp5 pp5 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/16)-2*floor(floor((time-10n)/10n)/32))-1)
Bp6 pp6 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/32)-2*floor(floor((time-10n)/10n)/64))-1)
Bp7 pp7 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/64)-2*floor(floor((time-10n)/10n)/128))-1)
Bp8 pp8 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/128)-2*floor(floor((time-10n)/10n)/256))-1)
Bp9 pp9 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/256)-2*floor(floor((time-10n)/10n)/512))-1)
Bp10 pp10 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/512)-2*floor(floor((time-10n)/10n)/1024))-1)
Bn1 pn1 0 V = 0.75 - 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/1)-2*floor(floor((time-10n)/10n)/2))-1)
Bn2 pn2 0 V = 0.75 - 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/2)-2*floor(floor((time-10n)/10n)/4))-1)
Bn3 pn3 0 V = 0.75 - 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/4)-2*floor(floor((time-10n)/10n)/8))-1)
Bn4 pn4 0 V = 0.75 - 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/8)-2*floor(floor((time-10n)/10n)/16))-1)
Bn5 pn5 0 V = 0.75 - 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/16)-2*floor(floor((time-10n)/10n)/32))-1)
Bn6 pn6 0 V = 0.75 - 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/32)-2*floor(floor((time-10n)/10n)/64))-1)
Bn7 pn7 0 V = 0.75 - 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/64)-2*floor(floor((time-10n)/10n)/128))-1)
Bn8 pn8 0 V = 0.75 - 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/128)-2*floor(floor((time-10n)/10n)/256))-1)
Bn9 pn9 0 V = 0.75 - 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/256)-2*floor(floor((time-10n)/10n)/512))-1)
Bn10 pn10 0 V = 0.75 - 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/512)-2*floor(floor((time-10n)/10n)/1024))-1)
.ic v(mp)=0.875 v(lp)=0.875 v(mn)=0.625 v(ln)=0.625
.tran 5n 10250n 0 5n uic
.print tran v(mp) v(mn)
.end
87 changes: 87 additions & 0 deletions specs/analog/decks/sar_cdac_half.cir
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SAR ADC split capacitive DAC, one half (x18 of the golden deck), ideal capacitors, 1024 codes in one run
* specs/analog/decks/sar_cdac_half.cir -- test data for specs/analog/sar_cdac.t27 (#10540). A plain netlist, no .control block.
* Topology of Diff_cap_DAC (the golden SAR ADC deck, subckt Diff_cap_DAC, lines 529-591): 31 unit capacitors from net1 (node l) to the LSB plates
* p1..p5 (1, 2, 4, 8, 16 units), one unit between net1 and Vout (node m), 31 unit capacitors from Vout to the MSB plates p6..p10 (1, 2, 4, 8, 16).
* Unit = 100 fF, ideal. Plate p_j is Bit_j. The tracking switch is not modelled: Vout and net1 start at the sampled 0.75 V (.ic, and IC=0 on every
* capacitor because every plate rests at VCM = 0.75 V and the bridge is uncharged). From 10 ns, interval n (n = 0..1023, 10 ns each) puts plate j
* at VDD = 1.5 V when bit j-1 of n is 1 and at 0 V when it is 0: the code is n, and the plates go straight from code n-1 to code n. The network is
* algebraic (capacitors only), so the settled voltage of an interval does not depend on the time grid; a B source declares no breakpoint.
* Read the LAST printed point inside each interval. Run: ngspice -b sar_cdac_half.cir (.print shows 7 digits; the spec's table was read with
* set numdgt=15 in a control block wrapped around this same netlist, so it holds the full float64 values).
C1_1 l p1 100f IC=0
C2_1 l p2 100f IC=0
C2_2 l p2 100f IC=0
C3_1 l p3 100f IC=0
C3_2 l p3 100f IC=0
C3_3 l p3 100f IC=0
C3_4 l p3 100f IC=0
C4_1 l p4 100f IC=0
C4_2 l p4 100f IC=0
C4_3 l p4 100f IC=0
C4_4 l p4 100f IC=0
C4_5 l p4 100f IC=0
C4_6 l p4 100f IC=0
C4_7 l p4 100f IC=0
C4_8 l p4 100f IC=0
C5_1 l p5 100f IC=0
C5_2 l p5 100f IC=0
C5_3 l p5 100f IC=0
C5_4 l p5 100f IC=0
C5_5 l p5 100f IC=0
C5_6 l p5 100f IC=0
C5_7 l p5 100f IC=0
C5_8 l p5 100f IC=0
C5_9 l p5 100f IC=0
C5_10 l p5 100f IC=0
C5_11 l p5 100f IC=0
C5_12 l p5 100f IC=0
C5_13 l p5 100f IC=0
C5_14 l p5 100f IC=0
C5_15 l p5 100f IC=0
C5_16 l p5 100f IC=0
C6_1 m p6 100f IC=0
C7_1 m p7 100f IC=0
C7_2 m p7 100f IC=0
C8_1 m p8 100f IC=0
C8_2 m p8 100f IC=0
C8_3 m p8 100f IC=0
C8_4 m p8 100f IC=0
C9_1 m p9 100f IC=0
C9_2 m p9 100f IC=0
C9_3 m p9 100f IC=0
C9_4 m p9 100f IC=0
C9_5 m p9 100f IC=0
C9_6 m p9 100f IC=0
C9_7 m p9 100f IC=0
C9_8 m p9 100f IC=0
C10_1 m p10 100f IC=0
C10_2 m p10 100f IC=0
C10_3 m p10 100f IC=0
C10_4 m p10 100f IC=0
C10_5 m p10 100f IC=0
C10_6 m p10 100f IC=0
C10_7 m p10 100f IC=0
C10_8 m p10 100f IC=0
C10_9 m p10 100f IC=0
C10_10 m p10 100f IC=0
C10_11 m p10 100f IC=0
C10_12 m p10 100f IC=0
C10_13 m p10 100f IC=0
C10_14 m p10 100f IC=0
C10_15 m p10 100f IC=0
C10_16 m p10 100f IC=0
Cbr l m 100f IC=0
B1 p1 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/1)-2*floor(floor((time-10n)/10n)/2))-1)
B2 p2 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/2)-2*floor(floor((time-10n)/10n)/4))-1)
B3 p3 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/4)-2*floor(floor((time-10n)/10n)/8))-1)
B4 p4 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/8)-2*floor(floor((time-10n)/10n)/16))-1)
B5 p5 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/16)-2*floor(floor((time-10n)/10n)/32))-1)
B6 p6 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/32)-2*floor(floor((time-10n)/10n)/64))-1)
B7 p7 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/64)-2*floor(floor((time-10n)/10n)/128))-1)
B8 p8 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/128)-2*floor(floor((time-10n)/10n)/256))-1)
B9 p9 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/256)-2*floor(floor((time-10n)/10n)/512))-1)
B10 p10 0 V = 0.75 + 0.75*u(time-10n)*(2*(floor(floor((time-10n)/10n)/512)-2*floor(floor((time-10n)/10n)/1024))-1)
.ic v(m)=0.75 v(l)=0.75
.tran 5n 10250n 0 5n uic
.print tran v(m)
.end
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