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analog: sar_cdac.t27 -- the SAR ADC split capacitive DAC with its 1-unit bridge, charge redistribution against ngspice (Closes #10540) - #10575
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…nit bridge, charge redistribution against ngspice (Closes #10540) M4a of the SAR ADC milestone (#10524, epic #10486). One half of Diff_cap_DAC of the golden SAR ADC deck: 31 LSB units on net1, a 1-unit bridge, 31 MSB units on Vout, unit counts and deck lines (529-591) pinned in the spec. Each bottom-plate switch event is M1's step (specs/analog/linear.t27) with D = 0 and N = K = C^-1 C_b, the Q.24 charge-transfer ratios derived in the tests from the counts two ways (adjugate and closed form) and stored as words. A code is ten events, Bit_10 first, plates moving +-VCM from the sampled state. Result for all 1024 codes of one half: - the deck's 1-unit bridge is the ideal bridge for its 31-unit LSB array (no dummy unit): every Vout ratio is exactly 2^(j-1)/1023, INL 0 - bridge-induced error is a gain term: (2c-1023)/2046 LSB against the nominal 10-bit half, max 0.5 LSB at codes 0 and 1023 (first at code 0) - arithmetic error vs the f64 closed form: 1.74 units of 2^-24 V (7.1e-5 LSB) - ngspice-47 with ideal capacitors (decks sar_cdac_half.cir, sar_cdac_diff.cir): 1.29e-12 V from the closed form, 1.74 units from the fixed point, every code - differential pair checked at 16 codes - the 32/31 bridge is ideal only with a dummy 32nd unit: with it bend 0 and gain error 0; on the deck's array it bends 0.94 LSB. Bit_8 with 3 units fails 7 of 12 tests (28.9 LSB of bend, 42 mV from ngspice) 12 tests, 0 vacuous, sealed (all hashes MATCH). Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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This was referenced Oct 18, 2026
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This was referenced Oct 18, 2026
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Closes #10540
M4a of the SAR ADC milestone (#10524, epic #10486). Adds
specs/analog/sar_cdac.t27(+ seal) and two ngspice decks inspecs/analog/decks/. No board top, no PDK capacitor model.What it is
One half of
Diff_cap_DACof the golden SAR ADC deck (read at run time, GPL-2.0, not vendored): 31 LSB units on net1 (Bit_1..Bit_5 = 1, 2, 4, 8, 16, deck lines 529-559), a 1-unit bridge (line 560), 31 MSB units on Vout (Bit_6..Bit_10, lines 561-591). Unit counts and line numbers are pinned in the spec and checked (FR-001).Each bottom-plate switch event is M1's step (
use analog::linear, nothing copied) with D = 0 and N = K = C^-1 C_b. K is derived in the tests from the counts two ways (adjugate and the closed form of the split array, agree to 1e-15) and stored as Q.24 words. A code is ten events, Bit_10 first, each plate moving +-VCM (0.75 V) from the sampled state, asDAC_control/neg_bottom_plate_logicdo: every plate rests at VCM, then goes once to VDD or 0 V. The N half is the P half reversed. The comparator is not modelled; the code is an input.Correction to the issue's premise (please read)
The issue expects the deck's 1-unit bridge to carry a half-to-half mismatch against an "ideal 32/31 bridge". The measurement says the deck's bridge IS the ideal one: the ideal bridge is CL/31, which is 1 unit for the deck's 31-unit LSB array (no dummy unit) and 32/31 only for an array with a 32nd, dummy unit to ground (the textbook split array). For the deck D = 3131 + 1(31+31) = 1023 and every Vout ratio is exactly 2^(j-1)/1023. The negative control "ideal bridge makes the error vanish" therefore holds for the dummy-unit array, not for the deck's; both are in the tests.
Bridge error (FR-002), all 1024 codes of one half
Cause: the bridge in series with the 31-unit array is 31/32 of a unit, so the top plate sees 1023/32 units instead of 32 and the staircase spans exactly VDD where a nominal half spans 1023/1024 of it.
Comparisons
Negative controls
Gates
t27c test-report specs/analog/sar_cdac.t27: 12 tests, 12 pass, 0 FAIL, vacuous passes 0 of 12 (runtime asserts per test 29, 21, 6, 17, 4100, 1032, 1034, 2067, 80, 1, 10, 16);tri test12/12t27c seal --savethen--verify: all hashes MATCH, saved with the zig cache set, 0 home paths in the sealpython3 -I tools/dupe_scan.py: ok;tri types ratchet: CLEAN 107/107 (structs areCdacNodesandCdacWorst, unique names)t27b-native-ratchetred with only UNLISTED rows for the new spec is expected (spec PRs do not edit the ledger, t27b ledger steward: the rules and the job card, so spec PRs stop editing the ledger (Closes #8654) #8656)Not covered
No IHP capacitor value or mismatch, parasitics, 4 fF loads, switch charge injection, settling or leakage; no comparator, SAR logic, eleventh decision or output code; no board. Differential spot codes leave the rails at the extremes (-0.125 V, 1.625 V) in the ideal linear model.
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