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t27f: frontend.t27 -- T27F is t27's frontend, every visual surface in one law, served by TRI CLAW (Closes #10537) - #10551

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t27f: frontend.t27 -- T27F is t27's frontend, every visual surface in one law, served by TRI CLAW (Closes #10537)#10551
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Closes #10537

The owner asked for everything visual to be gathered into one tool, T27F: t27's frontend, its own way of showing things, made through several tools. They also asked for T27F to go into TRI CLAW. This PR gives T27F one law, one definition, and pointers to that definition everywhere else.

What changes

Measured (Railway lab, 2026-10-19, master 6ea5f51 specs)

t27c test-report Passed Vacuous
specs/t27f/frontend.t27 7/7 0
specs/skills/t27-t27f.t27 1/1 (11 asserts) 0
spec_graph 14/14 0
topic_engine 14/14 0
quest 9/9 0
spec_graph_view 9/9 0
specs/t27mcp/service.t27 9/9 0
  • t27c seal --verify reports "all hashes MATCH" for frontend, spec_graph and igla/own_model_board, the deepest importer.
  • The spec_hash of t27f_T27fFrontend.json equals the sha256 of the spec, 13cd46e9....

Not claimed

  • Deployed /mcp mount not measured. Nobody has checked whether TRI CLAW's deployed /mcp mounts the t27 tools today. The spec states which tools it should carry; the wiring lives in gHashTag/999-multibots-telegraf.
  • claw/t27f is BLOCKED. It is skipped on PRs until the owner grants the App checks:write.
  • The particle reel and still are LAB. No MCP tool renders them yet, and no reel renderer lives in the repo.
  • Compiler defect found here:
    • The splicer resolves an imported function's internal calls by global name.
    • name_ok exists in both t27mcp/service.t27 and t27mcp/tool_schema.t27. So service::admit cannot be imported next to tool_schema: t27c gen reports "ambiguous, not spliced".
    • claw_serves therefore uses home_of. The defect belongs on epic: self-host t27c -- rewrite the compiler from Rust into t27 #5980.

🤖 Generated with Claude Code

@gHashTag @claude
t27f: frontend.t27 -- T27F is t27's frontend, every visual surface in…
20d7c38 
… one law, served by TRI CLAW (Closes #10537)

The owner asked that everything visual be gathered into one tool, T27F, the
frontend of t27, made through several tools, and that T27F go into TRI CLAW.

- specs/t27f/frontend.t27 (module T27fFrontend): 13 surfaces (spec graph,
  outline, map still, graph page, hot stream, check-run, preview, particle
  reel, still, map video, live particles, UI plan, dashboard), what draws each
  today, intent -> surface routing, a stand-in when the wanted surface cannot
  be made, claim_ok (nothing undrawn is claimed made), and which surfaces
  TRI CLAW serves through the t27 home of specs/t27mcp/service.t27.
- Skill t27f: renamed T27F Frontend; "What T27F is" redefined around the
  frontend, the spec diagram kept as its core; stale "What exists" rows fixed
  (graph page live, reels are surfaces, not applications).
- Pointers in CLAUDE.md, AGENTS.md, specs/OWNERS.md, four spec headers and
  the skill card specs/skills/t27-t27f.t27 now point at the new definition.
- 16 seals rewritten with t27c seal --save on the Railway lab; ledger row for
  frontend.t27.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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ledger: specs/analog/linear_zoh.t27 is t27b-blocked on ExprCall(@sin)…
714ad3c 
…; master merged it without a row (Closes #10537)

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Filed the splicer defect behind the home_of workaround in claw_serves: #10556 (epic #5980). Once it is fixed, claw_serves can call service::admit directly.

@gHashTag @claude
ledger: restore the t27b ledger and add the four analog rows master m…
f9e0b7f 
…erged without (Closes #10537)

The previous commit appended a row after every line because the insert
line number was empty. This puts the file back and adds bench, linear,
mos_table (pass) and linear_zoh (blocked on ExprCall(@sin)) in order.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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PR Dashboard

Generated at: 2026-10-18 17:55:03 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 47
PRs with All Checks Green 3
READY 0
FAILING 47
PENDING 0
NO CHECKS YET 0

These columns do not partition: 0 + 47 + 0 + 0 = 47, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=fad12492937a != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@github-actions github-actions Bot mentioned this pull request Oct 18, 2026
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gHashTag and others added 2 commits October 19, 2026 01:08
@gHashTag @claude
Merge origin/master into claude/t27f-frontend-10537 (Closes #10537)
848ad10 
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@gHashTag @claude
ledger: name the six specs master merged without a row; cap 134 -> 13…
6c0d218 
…6 for the two blocked ones (Closes #10537)

Evidence: the t27b-native-ratchet job of master run 90f6248 (fresh t27b built
from master) lists app-tabs, systolic, preflight, reset_queue and
t27mcp/visual_output as UNLISTED t27b pass, and kill_rule as blocked on
ExprCall(undeclared fn). linear_zoh (blocked on ExprCall(@sin)) was already
added on this branch. Non-pass rows are now 136, so max_not_pass equals
reality (loop-tools-tracked). Merged origin/master first (also brings the
Ring -> RingPeak rename 911166f).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Merge origin/master into claude/t27f-frontend-10537 (Closes #10537)
8b563f6 
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

# Conflicts:
#	.claude/skills/t27f/SKILL.md
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PR Dashboard

Generated at: 2026-10-18 19:44:02 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 44
PRs with All Checks Green 6
READY 0
FAILING 44
PENDING 0
NO CHECKS YET 0

These columns do not partition: 0 + 44 + 0 + 0 = 44, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=fad12492937a != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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gHashTag enabled auto-merge (squash) October 18, 2026 19:54
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Merge origin/master into claude/t27f-frontend-10537
80b9804 
Ledger conflict: kept master's sar_cdac row and this branch's frontend row.
Also adds the token_shape row (#10633, same line as #10634) so the
ratchet's last UNLISTED entry is named here too.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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PR Dashboard

Generated at: 2026-10-18 20:29:49 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 45
PRs with All Checks Green 5
READY 2
FAILING 45
PENDING 0
NO CHECKS YET 0

These columns do not partition: 2 + 45 + 0 + 0 = 47, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=fad12492937a != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@gHashTag
gHashTag merged commit 2d0c352 into master Oct 18, 2026
34 of 35 checks passed
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gHashTag added a commit that referenced this pull request Oct 18, 2026
@gHashTag @claude
Merge master up to 40b59d3 into fpga/cell26-ternary-matvec
0102386 
Every line comes from master. The two igla_own_model seals conflicted
because master's #10551 changed specs/t27f/topic_engine.t27 in their
closure. This merge keeps this branch's seals; the next commit reseals
both against the merged tree on the Railway lab (Refs #10461).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
gHashTag added a commit that referenced this pull request Oct 18, 2026
@gHashTag @claude
seals: reseal own_model and own_model_board after the master merge (R…
e337b6e 
…efs #10461)

Master's #10551 changed specs/t27f/topic_engine.t27, which is in the
closure of both seals. Resealed on the Railway lab with t27c built from
0102386: own_model.t27 10/10, own_model_board.t27 6/6, and t27c gen-json
still writes gen/json/igla/own_model_board.json byte for byte (sha256
3b2c0bce...b5cf).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
gHashTag added a commit that referenced this pull request Oct 18, 2026
@gHashTag @claude
fpga(ax7203): ternary mat-vec over real tern-tc-9m weights in DDR3, U…
39688f6 
…ART receipt (Closes #10461) (#10475)

* fpga(ax7203): ternary mat-vec over real tern-tc-9m weights in DDR3, UART receipt (Closes #10461)

Cell 26 of specs/igla/own_model.t27 (epic #10024), the compute step on top of
the DDR3 read path of #10248.

- specs/fpga/ddr3_ternary_matvec.t27: the board spec. It receives the 20,480
  bytes of blocks.0.attn.k.weight (tern-tc-9m, sha256 3102abdf...ce9c, offset
  10,589,476) on UART RX P20, packs them into 640 beats of 256 bits, writes them
  to DDR3, reads them back one beat at a time and steps through their trits one
  per clock: y_r = sum_c w_rc * x_c, x_c = int8(37c + 11), wrapping 32 bits.
  Receipt on N15: T27 TERN N= S= C= Y= E= F= L= PASS|FAIL.
- specs/fpga/tern9m_l0_k_weights.t27: the same bytes as 2,560 u64 words made
  with od, and the tests that compute S_EXPECT and Y_EXPECT from them with the
  board spec's own fold and trit_term; the FF-as-+1 mutant and a one-byte
  change both miss.
- Tests on the Railway lab: 9/9 and 5/5, 0 vacuous. A copy of the board spec
  with the FF trit read as +1 fails its own test.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* fpga: board_receipt.t27 holds the receipt pieces the AX7203 board specs shared (Refs #10461)

fold, hex_digit and the PASS/FAIL verdict characters were written three times,
in rc_filter_ax7203, ddr3_head_bandwidth and ddr3_ternary_matvec; dupe-bodies
named them. They now live in one pure module, specs/fpga/board_receipt.t27
(4 tests, 0 vacuous), and each board spec uses it. ddr3_head_bandwidth keeps
its own four-verdict verdict_char for the SLOW and KILL lines.

The head_bandwidth and rc_filter netlists emitted after the move equal the
ones from before it, up to line order, comments and the function name.

Seals written on the Railway lab with zig on PATH; three t27b ledger rows.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* dupe-bodies: drop the hex_digit group from the baseline (Refs #10461)

board_receipt.t27 now holds the one hex_digit the three AX7203 board specs
had each written, so the group is gone and the gate asked for the ceiling to
come down with it: 1 line removed by tools/dupe_scan.py --bless.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* elab ratchet: rows for board_receipt 0 and tern9m_l0_k_weights 8 (Refs #10461)

Both specs arrive with cell 26 and gen-verilog emits a module for each, so the
ratchet read them as NEW. board_receipt elaborates clean. The 8 in the weights
spec are all names it takes by `use` from board_receipt and from
ddr3_ternary_matvec (a t27b spec gen-verilog skips); the weights are test data
the board receives over the UART, never synthesized. Measured on CI (iverilog
12.0) and on the Railway lab (11.0): 214 errors, baseline now 214.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* ddr3_ternary_matvec: the board judges against S_EXPECT and Y_EXPECT out of reset (Refs #10461)

The first board run printed the right N, S, C and Y with E=F=0, and FAIL:
s_want and y_want reset to 0. The tests set them before each run, so the
spec passed while the hardware compared a correct receipt against 0.

Both registers now reset to the pinned constants (t27b emits them as the
reset values), and a new first test asserts the out-of-reset values before
any test assigns them. With the old `= 0` initializers that test fails; the
FF-as-+1 mutant still fails its trit test. 10/10 pass, 0 vacuous; seals
written on the Railway lab.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* tern9m_l0_k_weights: pin the two FAIL receipts the negative controls print (Refs #10461)

The mutant test only said Y != Y_EXPECT and the byte-0 test only said
S and Y differ. Both now also assert the exact values, read off the
spec's own failing assert_eq with 0 in their place, not off the board:

- Y_MUT_FF = 0x3E5E6C8ED51DF5C8, Y of the FF-as-+1 mutant on the real bytes
- S_FLIP0  = 0x4B58160720ABB81C, Y_FLIP0 = 0x9A50D884522C2320, the real
  design on the bytes with byte 0 changed from FF to 01

On the AX7203 the mutant bitstream printed Y=3E5E6C8ED51DF5C8 FAIL and
the design printed S=C=4B58160720ABB81C Y=9A50D884522C2320 FAIL, so
each negative control fails for the predicted reason.

5/5 pass, 0 vacuous (asserts 4, 3, 1, 2, 6); resealed on the Railway lab.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* own_model: cell 26 verified, compute from DDR3 on the AX7203 reviewed (Refs #10024, Refs #10461)

Cell 26 ("Full model on FPGA, DDR3") moves from draft to verified at 15
percent. specs/fpga/ddr3_ternary_matvec.t27 computes y = W x on the AX7203
from the tern-tc-9m layer-0 K weights held in DDR3. Its UART receipt equals
what the weights spec's test computes, and both negative controls print
FAIL.

Review 5565244743 is the reviewer bee on head 21ccad3. The model verdict
was approve, and it named each of the three red checks as master's. The bee
posted it as NEEDS_PERSON because the head changes seal files, the same
hold as review 5563181513 on #10428 (cell 9).

The board now reads 4 published, 23 verified, 0 drafts, 0 gaps; 62%.
own_model.t27 passes 10/10 and own_model_board.t27 passes 6/6, 0 vacuous,
on the Railway lab. The seals and gen/json/igla/own_model_board.json were
written there.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

* seals: reseal own_model and own_model_board after the master merge (Refs #10461)

Master's #10551 changed specs/t27f/topic_engine.t27, which is in the
closure of both seals. Resealed on the Railway lab with t27c built from
0102386: own_model.t27 10/10, own_model_board.t27 6/6, and t27c gen-json
still writes gen/json/igla/own_model_board.json byte for byte (sha256
3b2c0bce...b5cf).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

---------

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
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t27f: define T27F as t27's native visualization, through several tools, in every home

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