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verilog widths: why_card and deps_card edge buffers are exact widths, ledgered (Closes #10774) #10776

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verilog widths: why_card and deps_card edge buffers are exact widths, ledgered (Closes #10774) #10776

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16 changes: 16 additions & 0 deletions tools/verilog_width_baseline.txt
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Expand Up @@ -60,3 +60,19 @@ specs/claw/suggest_feed.t27
# renders 1080x1920 and 1920x1080 video on a host; it has no hardware form.
# Same class as big_frame.t27 and suggest_feed.t27.
specs/t27f/token_floor.t27
#
# specs/t27f/why_card.t27 and specs/t27f/deps_card.t27 -- not buses: each
# card's main reads the whole `t27c use-edges --specs-dir specs` output from
# stdin into one buffer, and that buffer is the only absurd signal in either
# spec. The width is exact:
#
# edges : [262144]u8 = 262144*8 = 2,097,152 bits -> [2097151:0]
#
# It cannot shrink under the gate: on master at #10774 the edge list was
# 2,490 lines, 138,986 bytes, already past 131,072 bytes (2^20 bits), and
# it grows with the corpus. Both mains are host text plumbing (std.c.read on
# fd 0, getenv, an ffmpeg filter graph on stderr) with no hardware form.
# Same class and same arithmetic as suggest_feed.t27; t27f precedent is
# token_floor.t27 (#10443).
specs/t27f/deps_card.t27
specs/t27f/why_card.t27
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