Repository navigation
verilog widths: why_card and deps_card edge buffers are exact widths, ledgered (Closes #10774) - #10776
Closed
gHashTag wants to merge 1 commit into
Closed
verilog widths: why_card and deps_card edge buffers are exact widths, ledgered (Closes #10774)#10776gHashTag wants to merge 1 commit into
gHashTag wants to merge 1 commit into
Conversation
… ledgered (Closes #10774) Master's absurd-width check has been red since #10719 and #10725. Measured on the lab: the only absurd signal in either spec is main's stdin buffer `edges : [262144]u8` = 2,097,152 bits -> [2097151:0], which is exact, not an accident. It holds the whole `t27c use-edges` output, already 138,986 bytes (past the 2^20-bit gate), so the buffer cannot shrink under the gate. Both mains are host text plumbing with no hardware form, the same class as suggest_feed.t27 (#10373) and token_floor.t27 (#10443). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
This was referenced Oct 19, 2026
Owner
Author
Contributor
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Closes #10774
What
Two ledger rows in
tools/verilog_width_baseline.txt, one each forspecs/t27f/why_card.t27andspecs/t27f/deps_card.t27. Each row carries its arithmetic. Nothing else changes.Why this is a ledger row and not a spec or compiler fix
Master's
Verilog widths (absurd-width ledger)check has been red since #10719 and #10725 merged (seen on #10387, job 117853026643). I measured both specs on the Railway lab with a t27c built from master:t27c gen-verilogisreg [2097151:0] edges;. It comes frommain's stdin buffervar edges : [262144]u8. 262144 * 8 = 2,097,152 bits, so the width is exact. 2^21 - 1 here is a byte count times eight, not a mask or a u21 max leaking into a width, and t27c inferred it correctly.t27c use-edges --specs-dir specsoutput. On master that output is 2,490 lines and 138,986 bytes, already more than 131,072 bytes (2^20 bits, the gate). A buffer small enough to pass the gate would make both cards refuse the real corpus, and the corpus only grows.mains are host text plumbing: they read fd 0 withstd.c.read, callgetenv, and print an ffmpeg filter graph to stderr. They have no hardware form.Precedent:
specs/claw/suggest_feed.t27(#10373, issue #10365) is already in the ledger for the same[262144]u8->[2097151:0]arithmetic.specs/t27f/token_floor.t27(#10443) is the t27f precedent for a host renderer's working memory. The new rows follow their form.Verification (Railway lab, master 797bd09 + this diff, t27c built from master)
tools/check_verilog_widths.py --require:scanned 2346 spec(s)...OK: 6 known, 0 new.t27c test-report specs/t27f/why_card.t27: pass 10, FAIL 0, vacuous passes 0 of 10t27c test-report specs/t27f/deps_card.t27: pass 17, FAIL 0, vacuous passes 0 of 17🤖 Generated with Claude Code