analog: mos_psp103.t27 -- IHP SG13G2 PSP103 tables for five corners from ngspice, run by M3a's solver, inverter against ngspice (Closes #10516)

.trinity/seals/analog_AnalogMosPsp103.json

@@ -0,0 +1,41 @@
+{
+  "built_by": "t27c-bootstrap@0.5.2+ea35d9b72",
+  "closure": [
+    {
+      "spec": "specs/analog/linear.t27",
+      "spec_hash": "sha256:3ddef7be183aba583ed285334ee389b48a65b41335e98914514235db7c4e5d62"
+    },
+    {
+      "spec": "specs/analog/mos_psp103_data.t27",
+      "spec_hash": "sha256:d5f3244ff1936f2b96e95b06e022d6b42b489ac49e025ec99486d6d36e6c6580"
+    },
+    {
+      "spec": "specs/analog/mos_table.t27",
+      "spec_hash": "sha256:9c0d1537ed5d8d60c4bdcb67d1e4c73ef80270e8cab224cb089c5b568fe11182"
+    }
+  ],
+  "config": "gen=c,rust,verilog,zig;tests=zig",
+  "gen_hash_c": "sha256:d7a49c643703a544723718186df74850018c4bf067fdb06ca9c860d775e069e8",
+  "gen_hash_rust": "sha256:32ee0d51345b936e45ff10956b90fdcafb6106bca46c2700de2bf43bf4407119",
+  "gen_hash_verilog": "sha256:0e3d19e85e67353129e8213c6135a5d1b518de4d7502c2d92512695b92de832e",
+  "gen_hash_zig": "sha256:445a5f05e794204ad3e4c198735c6fb1f4ab816e26fd36d3c408bba83168164f",
+  "module": "AnalogMosPsp103",
+  "ring": 12,
+  "seal_schema": 2,
+  "sealed_at": "2026-10-19T02:10:22Z",
+  "sealed_by": "t27c-bootstrap@0.5.2",
+  "spec_hash": "sha256:c5bd55a847953654fbef792dcfc61da7f6434b8023341df9ab4a53e5d082bbe0",
+  "spec_path": "specs/analog/mos_psp103.t27",
+  "tests": {
+    "failed": 0,
+    "failing": [],
+    "forced": false,
+    "passed": 11,
+    "total": 11,
+    "vacuous": 0
+  },
+  "toolchain": {
+    "test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
+    "zig": "0.16.0"
+  }
+}

.trinity/seals/analog_AnalogMosPsp103Data.json

@@ -0,0 +1,33 @@
+{
+  "built_by": "t27c-bootstrap@0.5.2+ea35d9b72",
+  "closure": [
+    {
+      "spec": "specs/analog/linear.t27",
+      "spec_hash": "sha256:3ddef7be183aba583ed285334ee389b48a65b41335e98914514235db7c4e5d62"
+    }
+  ],
+  "config": "gen=c,rust,verilog,zig;tests=zig",
+  "gen_hash_c": "sha256:d0135ebcf91901c442dc8a0c3e3a431f50a57cbc563d430a34e45e68392c9dfe",
+  "gen_hash_rust": "sha256:9dad368c2549f028ae0828213c7231a0e8ff613988ff42ce7d3aac6fcf9c4e52",
+  "gen_hash_verilog": "sha256:52f448d5fe93db1de3faa5fa13cb881486ec67a2ed17d1db475cd4d8d222ac82",
+  "gen_hash_zig": "sha256:1bdd4c520cb0864ffa3c4d2f7ce80418e7a0752e37610b81b4a000c528c413f9",
+  "module": "AnalogMosPsp103Data",
+  "ring": 12,
+  "seal_schema": 2,
+  "sealed_at": "2026-10-19T02:10:08Z",
+  "sealed_by": "t27c-bootstrap@0.5.2",
+  "spec_hash": "sha256:d5f3244ff1936f2b96e95b06e022d6b42b489ac49e025ec99486d6d36e6c6580",
+  "spec_path": "specs/analog/mos_psp103_data.t27",
+  "tests": {
+    "failed": 0,
+    "failing": [],
+    "forced": false,
+    "passed": 4,
+    "total": 4,
+    "vacuous": 0
+  },
+  "toolchain": {
+    "test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
+    "zig": "0.16.0"
+  }
+}

.trinity/seals/analog_AnalogMosTable.json

@@ -1,33 +1,33 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+9b556b7c3",
+  "built_by": "t27c-bootstrap@0.5.2+ea35d9b72",
   "closure": [
     {
       "spec": "specs/analog/linear.t27",
       "spec_hash": "sha256:3ddef7be183aba583ed285334ee389b48a65b41335e98914514235db7c4e5d62"
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
-  "gen_hash_c": "sha256:a4c0ec9ec8298af635a1cb7363b0b9644b99f7f0a1b80bd709fb8b14184a82fb",
-  "gen_hash_rust": "sha256:d0cbeb4b09d5da7c886eaeefaa2c395a2b699b643a1b25bb7372c62d857f0d87",
-  "gen_hash_verilog": "sha256:97d7e477baee00d846fc850c5888d0fbbf7cf9c072124ee4f55e4b76eeffc851",
-  "gen_hash_zig": "sha256:d9752320d155e8ace406d0008627ea48410160f8b25eea9eb424b9e10eb4d540",
+  "gen_hash_c": "sha256:3de4432818944eab74fae03952b4b4cffd104b00b9cda80dd73bb6ed6e819f0c",
+  "gen_hash_rust": "sha256:775c36a7f0370d1bc3dd0752f72f435e3fbc6e4972ad9b5c77efc35fb2784750",
+  "gen_hash_verilog": "sha256:0f3b42817e930cb80890ec45f5ecb5ecdf2a73bb764d029149ab8519dfd43dfc",
+  "gen_hash_zig": "sha256:05393568aa75f13169560fb6fd1118d46141ae46931458fc181ac12ba42ca196",
   "module": "AnalogMosTable",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-18T16:22:23Z",
+  "sealed_at": "2026-10-19T02:09:56Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
-  "spec_hash": "sha256:168cd93374cec92ece02ddab1be51f49308d9efd3288ac0427f912d4a7521782",
+  "spec_hash": "sha256:9c0d1537ed5d8d60c4bdcb67d1e4c73ef80270e8cab224cb089c5b568fe11182",
   "spec_path": "specs/analog/mos_table.t27",
   "tests": {
     "failed": 0,
     "failing": [],
     "forced": false,
-    "passed": 13,
-    "total": 13,
+    "passed": 14,
+    "total": 14,
     "vacuous": 0
   },
   "toolchain": {
-    "test_runner": "sha256:1982ae948e24d00c5d221ccec12dfce1eb01204b53e37b0f857f93b16d64629d",
+    "test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
     "zig": "0.16.0"
   }
 }

.trinity/seals/analog_AnalogSarComparator.json

@@ -1,13 +1,13 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+9b556b7c3",
+  "built_by": "t27c-bootstrap@0.5.2+ea35d9b72",
   "closure": [
     {
       "spec": "specs/analog/linear.t27",
       "spec_hash": "sha256:3ddef7be183aba583ed285334ee389b48a65b41335e98914514235db7c4e5d62"
     },
     {
       "spec": "specs/analog/mos_table.t27",
-      "spec_hash": "sha256:168cd93374cec92ece02ddab1be51f49308d9efd3288ac0427f912d4a7521782"
+      "spec_hash": "sha256:9c0d1537ed5d8d60c4bdcb67d1e4c73ef80270e8cab224cb089c5b568fe11182"
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
@@ -18,7 +18,7 @@
   "module": "AnalogSarComparator",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-18T18:44:35Z",
+  "sealed_at": "2026-10-19T02:10:33Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
   "spec_hash": "sha256:2df42ed0afe41add0b43762dfa05c8aa38ecbc022bea8f7bbd72f55917bcb806",
   "spec_path": "specs/analog/sar_comparator.t27",

specs/analog/decks/psp103_inv_be.cir

@@ -0,0 +1,45 @@
+IHP SG13G2 inverter, 10 pF, backward Euler on a fixed 2 ns grid, corner mos_tt
+* specs/analog/decks/psp103_inv_be.cir -- reference data for specs/analog/mos_psp103.t27 (M3b, #10516, epic #10486). A netlist plus a
+* .control block that prints the numbers.
+* Circuit: the inverter of the uberWAVE golden SAR deck (PMOS w=3.0u l=0.45u, NMOS w=1.0u l=0.45u, both sg13_lv, ng=1, m=1; Vdd 1.5 V),
+* a lumped load of 10 pF on the output, no other element. Model, corner and temperature as in psp103_tab_tt.cir (IHP-Open-PDK commit
+* 21133f219b1a6da10d803e345761e77415ceff40, mos_tt, 27 C). dt = 2 ns, so dt / C = 200 V/A, the scale of the tables in
+* mos_psp103_data.t27. The device capacitances of PSP103 (gate-drain overlap and channel, drain junctions), which the table model does not
+* have, are a few fF to some ten fF: about 0.2 % of 10 pF. psp103_inv_be_500f.cir is the same run at 500 fF, where they are 20 times
+* larger in proportion.
+* Paths are NOT in this file: ngspice reads IHP_PDK (the IHP-Open-PDK checkout) and IHP_OSDI (the directory with the compiled
+* psp103.osdi and psp103_nqs.osdi) from the environment.
+* Run: IHP_PDK=<checkout> IHP_OSDI=<osdi dir> ngspice -b psp103_inv_be.cir > psp103_inv_be.out    (ngspice-47)
+* The input is a B source of nint(time / dt), a staircase that declares no breakpoint: Vdd (the output rests near 0 V) up to the
+* grid point 2 ns, 0 V from 3 ns (nint = 2) up to 403 ns, Vdd again from 403 ns (nint = 202). ngspice opens the run with steps of
+* tstep / 100 that double up to tmax; tstep = 0.78125 dt makes the first step 15.625 ps and the end of that ramp exactly dt = 2 ns, so every
+* internal point from then on is a multiple of 2 ns. Step k (k = 0..399) of the spec ends at (k + 2) dt and sees the input of nint =
+* k + 2: 0 V for k < 200, Vdd from k = 200. Integration: gear with maxord 1 is backward Euler; trtol = 1e7 stops the truncation test
+* from shrinking a step; reltol, vntol and abstol are tight enough for 1e-6 V and loose enough for Newton to converge at the input steps.
+* tstop is two steps past the last row used: ngspice splits a last step that would pass tstop, and that would move the last row.
+* What it prints: between "BEGIN tran_be" and "END tran_be", 401 rows "<index> TAB <time> TAB <y>": y is the output in units of 2^-24 V
+* (nint(v * 16777216)) at t = 2 ns, 4 ns, ... 802 ns: row 0 is the circuit at rest (t = dt, before step 0), row k + 1 is the output
+* after step k. They are the rows 8 to 408 of the run (rows 0 to 7 are the opening ramp, t < dt). The spec holds the y column.
+.lib $IHP_PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+VDD vdd 0 1.5
+Bin in 0 V = 1.5*(1-min(max(nint(time/2e-9)-1,0),1)+min(max(nint(time/2e-9)-201,0),1))
+XIP out in vdd vdd sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+XIN out in 0 0 sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+CL out 0 10p
+.temp 27
+.options method=gear maxord=1 trtol=1e7 reltol=1e-6 vntol=1e-9 abstol=1e-12 itl4=200
+.tran 1.5625n 804n 0 2n
+.control
+pre_osdi $IHP_OSDI/psp103.osdi
+pre_osdi $IHP_OSDI/psp103_nqs.osdi
+set numdgt=10
+set noprintscale
+run
+let y = nint(v(out) * 16777216)
+let ts = time[8,408]
+let ys = y[8,408]
+echo BEGIN tran_be
+print ts ys
+echo END tran_be
+.endc
+.end

specs/analog/decks/psp103_inv_be_500f.cir

@@ -0,0 +1,30 @@
+IHP SG13G2 inverter, 500 fF, backward Euler on a fixed 100 ps grid, corner mos_tt
+* specs/analog/decks/psp103_inv_be_500f.cir -- reference data for specs/analog/mos_psp103.t27 (M3b, #10516, epic #10486). A netlist plus
+* a .control block that prints two numbers.
+* The circuit and the run of psp103_inv_be.cir with the load at 500 fF and dt = 100 ps (dt / C = 200 V/A again, so the table model runs the
+* same 400 steps, bit for bit; only the circuit is 20 times faster). The device capacitances of PSP103 (gate-drain overlap and channel,
+* drain junctions: a few fF to some ten fF at W = 1 um and 3 um), which the table model does not have, are now a few percent of the load.
+* Paths are NOT in this file: ngspice reads IHP_PDK and IHP_OSDI from the environment (see psp103_tab_tt.cir).
+* Run: IHP_PDK=<checkout> IHP_OSDI=<osdi dir> ngspice -b psp103_inv_be_500f.cir    (ngspice-47)
+* Grid: tstep = 0.78125 dt makes the opening ramp end exactly at dt = 100 ps, so every internal point from then on is a multiple of dt. The
+* input is a B source of nint(time / dt): Vdd up to index 1, 0 V from index 2 (150 ps) to index 201, Vdd from index 202. Step k of the spec ends
+* at (k + 2) dt; step 0 starts at t = dt = 100 ps and step 200 at 201 dt = 20.1 ns.
+* What it prints (ngspice .meas, 6 digits, in s): tplh and tphl, the times at which the output crosses 0.75 V rising (after step 0's edge) and
+* falling (after step 200's edge); the delays are these minus 100 ps and minus 20.1 ns.
+.lib $IHP_PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+VDD vdd 0 1.5
+Bin in 0 V = 1.5*(1-min(max(nint(time/1e-10)-1,0),1)+min(max(nint(time/1e-10)-201,0),1))
+XIP out in vdd vdd sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+XIN out in 0 0 sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+CL out 0 500f
+.temp 27
+.options method=gear maxord=1 trtol=1e7 reltol=1e-6 vntol=1e-9 abstol=1e-12 itl4=200
+.tran 78.125p 40.4n 0 100p
+.meas tran tplh when v(out)=0.75 rise=1
+.meas tran tphl when v(out)=0.75 fall=1
+.control
+pre_osdi $IHP_OSDI/psp103.osdi
+pre_osdi $IHP_OSDI/psp103_nqs.osdi
+run
+.endc
+.end

specs/analog/decks/psp103_inv_fine.cir

@@ -0,0 +1,40 @@
+IHP SG13G2 inverter, 10 pF, converged reference (trapezoidal rule, steps of at most 20 ps), corner mos_tt
+* specs/analog/decks/psp103_inv_fine.cir -- reference data for specs/analog/mos_psp103.t27 (M3b, #10516, epic #10486). A netlist plus a
+* .control block that prints the numbers.
+* The circuit of psp103_inv_be.cir (inverter of the uberWAVE golden SAR deck, 10 pF, mos_tt, 27 C, IHP-Open-PDK commit 21133f21), run
+* the way ngspice runs by default: trapezoidal rule, local-error step control, but with the step held to 20 ps (1/100 of the 2 ns grid) so
+* that the grid of the fixed-step run is resolved a hundred times over. This is the continuous circuit as far as the spec needs it; the
+* difference between psp103_inv_be.cir and this run is the DISCRETIZATION error of backward Euler at dt = 2 ns.
+* The input is the same two edges as an ideal step: Vdd to 0 V at t = 2 ns (the start of step 0 of the fixed-step run, whose input is
+* evaluated at the end of the step) and 0 V to Vdd at t = 402 ns (the start of step 200).
+* Paths are NOT in this file: ngspice reads IHP_PDK and IHP_OSDI from the environment (see psp103_tab_tt.cir).
+* Run: IHP_PDK=<checkout> IHP_OSDI=<osdi dir> ngspice -b psp103_inv_fine.cir > psp103_inv_fine.out    (ngspice-47)
+* What it prints. tplh and tphl: the times at which the output crosses 0.75 V rising and falling (ngspice .meas, 6 digits, in s); the
+* delays are these minus 2 ns and minus 402 ns. Between "BEGIN tran_fine" and "END tran_fine", 401 rows "<index> TAB <y>": the output in units
+* of 2^-24 V, resampled by linearize onto the 2 ns grid, at t = 2 ns (row 0, at rest), 4 ns, ... 802 ns (row 400): the rows of the fixed-step
+* run, one for one. tstop is two steps past the last row used.
+.lib $IHP_PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+VDD vdd 0 1.5
+Bin in 0 V = 1.5*(1-u(time-2n)+u(time-402n))
+XIP out in vdd vdd sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+XIN out in 0 0 sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+CL out 0 10p
+.temp 27
+.options reltol=1e-6 vntol=1e-9 abstol=1e-12 itl4=200
+.tran 2n 804n 0 20p
+.meas tran tplh when v(out)=0.75 rise=1
+.meas tran tphl when v(out)=0.75 fall=1
+.control
+pre_osdi $IHP_OSDI/psp103.osdi
+pre_osdi $IHP_OSDI/psp103_nqs.osdi
+set numdgt=10
+set noprintscale
+run
+linearize v(out)
+let y = nint(v(out) * 16777216)
+let ys = y[1,401]
+echo BEGIN tran_fine
+print ys
+echo END tran_fine
+.endc
+.end

specs/analog/decks/psp103_inv_fine_500f.cir

@@ -0,0 +1,25 @@
+IHP SG13G2 inverter, 500 fF, converged reference (trapezoidal rule, steps of at most 1 ps), corner mos_tt
+* specs/analog/decks/psp103_inv_fine_500f.cir -- reference data for specs/analog/mos_psp103.t27 (M3b, #10516, epic #10486). A netlist plus
+* a .control block that prints two numbers.
+* The circuit of psp103_inv_be_500f.cir run with the step held to 1 ps (1/100 of the 100 ps grid), edges as ideal steps at t = 100 ps and
+* t = 20.1 ns (the starts of steps 0 and 200 of the fixed-step run).
+* Paths are NOT in this file: ngspice reads IHP_PDK and IHP_OSDI from the environment (see psp103_tab_tt.cir).
+* Run: IHP_PDK=<checkout> IHP_OSDI=<osdi dir> ngspice -b psp103_inv_fine_500f.cir    (ngspice-47)
+* What it prints (ngspice .meas, 6 digits, in s): tplh and tphl, the 0.75 V crossings; the delays are these minus 100 ps and minus 20.1 ns.
+.lib $IHP_PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+VDD vdd 0 1.5
+Bin in 0 V = 1.5*(1-u(time-100p)+u(time-20.1n))
+XIP out in vdd vdd sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+XIN out in 0 0 sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+CL out 0 500f
+.temp 27
+.options reltol=1e-6 vntol=1e-9 abstol=1e-12 itl4=200
+.tran 100p 40.4n 0 1p
+.meas tran tplh when v(out)=0.75 rise=1
+.meas tran tphl when v(out)=0.75 fall=1
+.control
+pre_osdi $IHP_OSDI/psp103.osdi
+pre_osdi $IHP_OSDI/psp103_nqs.osdi
+run
+.endc
+.end

specs/analog/decks/psp103_tab_ff.cir

@@ -0,0 +1,86 @@
+IHP SG13G2 PSP103 tables, corner mos_ff
+* specs/analog/decks/psp103_tab_ff.cir -- table data for specs/analog/mos_psp103_data.t27 (M3b, #10516, epic #10486). A netlist plus a
+* .control block that prints the numbers. The same deck exists for the other corners (psp103_tab_ff.cir, _ss, _fs, _sf); they differ in
+* the title, the .lib section, and in the held-out points: the tt deck prints mid_n and mid_p and 1000 R2 points, the others no midpoints and
+* the first 200 R2 points. The IHP corner file is read at run time and never copied here.
+* Model: IHP-Open-PDK commit 21133f219b1a6da10d803e345761e77415ceff40, ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib (PSP 103.6,
+* revision 200310), section mos_ff; the model code is libs.tech/verilog-a/psp103/psp103.va of the same commit, compiled with
+* OpenVAF-Reloaded v24.0.2mob to psp103.osdi (and psp103_nqs.osdi). Temperature 27 C (TNOM 27 C). Devices: sg13_lv_nmos w=1.0u l=0.45u
+* ng=1 m=1 and sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1, the W and L of the inverter in the uberWAVE golden SAR deck (its text is not copied).
+* Solver options: reltol 1e-6, vntol 1e-9, abstol 1e-14 (with ngspice's default tolerances the nested sweeps come out up to 0.1 % off).
+* Paths are NOT in this file. ngspice reads two environment variables: IHP_PDK, the IHP-Open-PDK checkout, and IHP_OSDI, the directory that
+* holds the compiled psp103.osdi and psp103_nqs.osdi.
+* Run: IHP_PDK=<checkout> IHP_OSDI=<osdi dir> ngspice -b psp103_tab_ff.cir > psp103_tab_ff.out    (ngspice-47)
+* What it prints. Between "BEGIN name" and "END name" every row "<index> TAB <value>" is one number, in sweep order (the first sweep
+* source runs fastest). The values are pasted into the spec in that order, none changed.
+*   grid_n  Id of the nmos at Vgs = ix * 62.5 mV, Vds = iy * 62.5 mV, ix and iy 0..24, 625 rows, ix outer. Id is in table units:
+*           nint(Id * 200 V/A * 2^24 units/V), the current times dt/C (200 V/A) in units of 2^-24 V (59.6 nV), so one unit is 0.298 nA.
+*           Negative values (the gate current that leaves through the drain at Vds = 0, at most 2 units) are held at 0: the table is unsigned.
+*   grid_p  the same for the pmos at Vsg = ix * 62.5 mV, Vsd = iy * 62.5 mV (source and bulk on the 1.5 V rail; the current that leaves
+*           the drain), 625 rows.
+*   inv_dc  the inverter's output (units of 2^-24 V) at Vin = 0, 31.25 mV, ... 1.5 V, 49 rows: the DC transfer of the same two devices.
+*   mid_n, mid_p  (tt only) Id in pA (nint(Id * 1e12)) at the 576 cell midpoints Vgs, Vds = (i + 1/2) * 62.5 mV, i = 0..23 (outer
+*           index the gate), the places a chord is worst: held-out points, never on a table node.
+*   r2_n, r2_p  Id in pA at held-out points of the R2 low-discrepancy sequence: point k is Vgs (Vsg) = 1.5 frac(k a1), Vds (Vsd) =
+*           1.5 frac(k a2), a1 = 0.7548776662466927, a2 = 0.5698402909980532, k = 1..1000 (1..200 in the other corners).
+* nmos table device: drain VDN, gate VGN, source and bulk at 0 V
+.lib $IHP_PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_ff
+VDN dn 0 0
+VGN gn 0 0
+XMN dn gn 0 0 sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+* pmos table device: source and bulk at the 1.5 V rail, drain VDP and gate VGP, both swept downward from 1.5 V
+VSP sp 0 1.5
+VDP dp 0 1.5
+VGP gp 0 1.5
+XMP dp gp sp sp sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+* the inverter
+VDD vdd 0 1.5
+VIN in 0 0
+XIP out in vdd vdd sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+XIN out in 0 0 sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+* held-out points: B sources compute the R2 point from the sweep variable k; the zero-volt sources VRDN, VRDP measure the drain current
+VK k 0 1
+BRGN rgn 0 V = 1.5*(v(k)*0.7548776662466927-floor(v(k)*0.7548776662466927))
+BRDN rdn0 0 V = 1.5*(v(k)*0.5698402909980532-floor(v(k)*0.5698402909980532))
+VRDN rdn0 rdn 0
+XRN rdn rgn 0 0 sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+BRGP rgp 0 V = 1.5-1.5*(v(k)*0.7548776662466927-floor(v(k)*0.7548776662466927))
+BRDP rdp0 0 V = 1.5-1.5*(v(k)*0.5698402909980532-floor(v(k)*0.5698402909980532))
+VRDP rdp rdp0 0
+VRSP rsp 0 1.5
+XRP rdp rgp rsp rsp sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+.temp 27
+.options reltol=1e-6 vntol=1e-9 abstol=1e-14
+.control
+pre_osdi $IHP_OSDI/psp103.osdi
+pre_osdi $IHP_OSDI/psp103_nqs.osdi
+set numdgt=10
+set noprintscale
+echo BEGIN grid_n
+dc VDN 0 1.5 0.0625 VGN 0 1.5 0.0625
+let u = nint(-i(VDN) * 200 * 16777216)
+let u = (u + abs(u)) / 2
+print u
+echo END grid_n
+echo BEGIN grid_p
+dc VDP 1.5 0 -0.0625 VGP 1.5 0 -0.0625
+let u = nint(i(VDP) * 200 * 16777216)
+let u = (u + abs(u)) / 2
+print u
+echo END grid_p
+echo BEGIN inv_dc
+dc VIN 0 1.5 0.03125
+let u = nint(v(out) * 16777216)
+print u
+echo END inv_dc
+echo BEGIN r2_n
+dc VK 1 200 1
+let u = nint(i(VRDN) * 1e12)
+print u
+echo END r2_n
+echo BEGIN r2_p
+let u = nint(i(VRDP) * 1e12)
+print u
+echo END r2_p
+.endc
+.end