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analog: mos_psp103.t27 -- IHP SG13G2 PSP103 tables for five corners from ngspice, run by M3a's solver, inverter against ngspice (Closes #10516) - #10778
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…rom ngspice, run by M3a's solver, inverter against ngspice (Closes #10516) M3b of the analog emulation epic (#10486). Id(Vgs, Vds) of sg13_lv_nmos (W 1.0 um) and sg13_lv_pmos (W 3.0 um), L 0.45 um, from ngspice-47 with PSP 103.6 over OSDI, IHP-Open-PDK commit 21133f21, 27 C, for mos_tt, mos_ff, mos_ss, mos_fs and mos_sf: 25 x 25 nodes of 62.5 mV over 0 .. 1.5 V, which is M3a's reader exactly. The decks (specs/analog/decks/psp103_*.cir) print the numbers, rounded to table units by ngspice itself; mos_psp103_data.t27 holds them with order-sensitive pins; mos_psp103.t27 judges them. mos_table.t27 changes only so that the solver takes the NMOS table and the PMOS table as two arguments (g_resid, newton_iter, inv_step, board_step, run_fix, newton_iter_f, run_tabf); every M3a test passes the same table twice and its pinned run is unchanged bit for bit. A new test checks the mirror with two different tables. sar_comparator.t27 is untouched; its seal is renewed because the closure hash of mos_table.t27 moved. Measured against ngspice tt: Id at 576 midpoints and 1000 R2 points per device within 6.5e-7 A (NMOS) and 4.4e-7 A (PMOS), relative error 0.56 % / 0.41 % where Id >= 100 uA; the proposed 1 % with a floor of 1e-9 A is NOT met (0.55 .. 0.73, weak inversion). DC transfer of the inverter within 5.5 mV and 11 uV of trip point (every corner within 6.6 mV and 0.26 mV). Transient at 10 pF, 400 steps: arithmetic 4.8 units, table + model 1.28 mV and 0.14 / 0.17 % of the delay, discretization 14.4 mV and 0.5 / 0.7 %. The gap to ngspice at 500 fF is 3.1 / 3.6 % and scales with 1 / C: it is the device capacitance, which these current-only tables lack. Negative controls: ss tables used as tt, any other corner used as tt, and the tables in the wrong slots all fail the tt check. test-report: 14 + 4 + 11 pass, 0 vacuous. Left for the charge tables and the weak-inversion read: see #10777. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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… and sar_switch (Closes #10753) M3b changed mos_table.t27 (two tables) and renewed sar_comparator's seal for its closure; this branch changed sar_comparator.t27 itself. The only conflict was that seal: both seals are made again on the merged tree. mos_table 14/14, sar_comparator 20/20, sar_switch 14/14, mos_psp103 11/11, mos_psp103_data 4/4, 0 vacuous each; seal --verify all MATCH; every closure hash current; dupe_scan ok. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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What
M3b of #10486. The IHP SG13G2
sg13_lv_nmos/sg13_lv_pmosPSP103 current tables, one pair per corner (tt ff ss fs sf), made by ngspice-47 and run by M3a's solver (specs/analog/mos_table.t27) in place of the square law, and the CMOS inverter checked against ngspice with the same model. Closes #10516.Three specs and nine decks:
specs/analog/mos_psp103_data.t27-- the numbers only (6250 table words, 245 inverter DC points, 4752 held-out currents, 802 waveform samples) with order-sensitive pins, as M3a pins its run. 4 tests.specs/analog/mos_psp103.t27-- the held-out statistics, the DC bisection, the delay crossings, the tt check and its negative controls. 11 tests. Nothing is copied from M3a; its reader, Newton step and run areused.specs/analog/mos_table.t27-- one change: the solver takes the NMOS tabletnand the PMOS tabletpas two arguments (g_resid,newton_iter,inv_step,board_step,run_fix,newton_iter_f,run_tabf). Every M3a test passes the same table twice (the call sites changed, nothing else): the pinned run (EXP_S) and all 13 old tests give what they gave, and one new test checks the mirror with two different tables.sar_comparator.t27is untouched (it uses none of those names); its seal is renewed because the closure hash ofmos_table.t27moved (thebuilt_byfield shows the compiler build I used).specs/analog/decks/psp103_tab_{tt,ff,ss,fs,sf}.cir,psp103_inv_{be,fine}.cir,psp103_inv_{be,fine}_500f.cir-- plain netlists with a.controlblock that prints the numbers.The tables
21133f219b1a6da10d803e345761e77415ceff40,cornerMOSlv.lib(PSP 103.6 rev 200310),psp103.vacompiled by OpenVAF-Reloaded v24.0.2mob; ngspice-47IHP_PDKandIHP_OSDIfrom the environmentgm and gds come from the same nodes as the value (FR-002): across every one of the 576 cells of each of the ten tables the interpolant moves by
gm_cell/gds_cellto within 2 units (5760 cell checks). Every table is nondecreasing along both axes, zero at Vds = 0 (the gate current that leaves through the drain, at most 2 units, is held at 0 by the deck), has an off current of at most 10 units, and the corners are in the foundry's order (fs: fast NMOS, slow PMOS; trip points fs < ff < tt < ss < sf).Interpolation error against ngspice (a test, both sides)
Held-out points are never nodes: tt has the 576 cell midpoints (where a chord is worst) and 1000 points of the R2 sequence per device; the other corners the first 200 R2 points.
ff ss fs sf: absolute at most 5.7e-7 A (NMOS) and 4.4e-7 A (PMOS), relative for Id >= 100 uA at most 0.38 % and 0.26 %.
The proposal of #10516 (1 %, floor 1e-9 A) is not met, and cannot be by a chord over a 62.5 mV cell. In weak inversion Id grows by a factor of about 6 per cell, where the chord at the midpoint is 43 % off, and below a few nA the rounding to 0.298 nA is a tenth of the current. 1 % holds where Id >= 100 uA. The bounds in the test are the measured ones. A finer grid or a log-domain read is in #10777.
The inverter against ngspice
DC transfer, 49 points (Vin = k * 31.25 mV), tables against ngspice, every corner:
| | worst |dVout| | trip point (0.75 V crossing) shift |
|---|---|---|
| tt | 5.48 mV (bound 5.51) | 11 uV (bound 12.5) |
| ff / ss / fs / sf | 6.3 / 4.2 / 6.6 / 4.0 mV | 71 / 48 / 255 / 196 uV (bound 266) |
Transient, tt, 400 steps: gate at Vdd and the output at rest, gate to 0 V at step 0, back to Vdd at step 200; C = 10 pF, dt = 2 ns (dt/C = 200 V/A). The fixed-point model is M3a's
run_fixwith K = 3 Newton iterations; its last residual is at most 1 unit at every step (bound 2).THE THREE ERRORS, kept apart:
All three together, the model against ngspice's converged run: tpLH 26.04 ns vs 25.94 ns (0.37 %), tpHL 19.63 ns vs 19.53 ns (0.51 %); the model's error and the scheme's partly cancel.
Most of the "table + model" row is not the table. The same 400 steps (dimensionless) against the same circuit at 500 fF / 100 ps: the model is 3.09 % / 3.63 % faster than ngspice backward Euler. The gap grows 21.8 and 21.1 times for a load 20 times smaller, i.e. it scales with 1/C: it is the device capacitance (gate-drain, drain junctions), which these current-only tables do not have. Charge tables are #10777.
Negative controls (tests that pass by seeing the failure)
check_ttholds a table pair to the tt bounds: Id at the 1000 R2 points of each device, the DC transfer and the 10 pF transient against ngspice tt.Checks run
t27c test-report: mos_table 14/14, mos_psp103_data 4/4, mos_psp103 11/11,vacuous passes 0in each (about 15 s, 11 s, 16 s warm).t27c seal --savethen--verify: all hashes MATCH for the four renewed or new seals; no home path and no blocked verdict in them.tools/dupe_scan.py: ok, no new duplicate body.tools/check_seal_currency.py: 0 stale.t27c check-calls --specs-dir specs/analog: 0.check_assertionless_spec_tests.py: ok.$TMPDIR(not committed); ngspice itself rounds each current to table units (nintin the deck) and clamps the sign.t27b-native-ratchetmay show UNLISTED rows for the two new specs; spec PRs do not edit the ledger (t27b ledger steward: the rules and the job card, so spec PRs stop editing the ledger (Closes #8654) #8656).What this does not claim
may_claim_speedupinbench.t27stays no), no power, no board: no bitstream, BRAM, LUT, DSP, Fmax or UART line.Left
#10777: terminal-charge tables, and a table read that is accurate in weak inversion (the 1 % proposal).
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