t27o: second golden port -- csr_map.rs to specs/host/csr_map.t27

.trinity/seals/host_HostCsrMap.json

@@ -0,0 +1,33 @@
+{
+  "built_by": "t27c-bootstrap@0.5.2+fccd4855e",
+  "closure": [
+    {
+      "spec": "specs/tools/t27o/rust_std.t27",
+      "spec_hash": "sha256:e72606b4b3d7611883db25ed9fdaecb4353fe6a1fef551500b3cd1cc18cceb79"
+    }
+  ],
+  "config": "gen=c,rust,verilog,zig;tests=zig",
+  "gen_hash_c": "sha256:083cb1f5e726bd722306785233f593cb7c383cc9f9c5a41d254817dee62b862e",
+  "gen_hash_rust": "sha256:6db01cb48cc05157355292e94a670d6d21ebfbe8263678b465a8651990679a6d",
+  "gen_hash_verilog": "sha256:ecac16d02fa5392b02b0adb2b12c7e79ec37e63c84b945c1fa6611377332bf1f",
+  "gen_hash_zig": "sha256:47feeaeb2df8fe3446776e3e5b040e49d1256ee9562092aabd3b50299dd86479",
+  "module": "HostCsrMap",
+  "ring": 12,
+  "seal_schema": 2,
+  "sealed_at": "2026-10-20T06:41:08Z",
+  "sealed_by": "t27c-bootstrap@0.5.2",
+  "spec_hash": "sha256:b8539174ecd40c855146c67863566ef825969f9f7793413dbbb8a394cc239f08",
+  "spec_path": "specs/host/csr_map.t27",
+  "tests": {
+    "failed": 0,
+    "failing": [],
+    "forced": false,
+    "passed": 13,
+    "total": 13,
+    "vacuous": 0
+  },
+  "toolchain": {
+    "test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
+    "zig": "0.16.0"
+  }
+}

bootstrap/gen/rust/host/csr_map.rs

@@ -0,0 +1,108 @@
+// Generated from .t27 spec
+// DO NOT EDIT — generated by t27c
+// NOT LOWERED BY THIS BACKEND: 13 test(s), 0 invariant(s), 0 function(s) with no body.
+// This backend emits declarations only. The spec's checks live in
+// the Zig and Verilog outputs; do not read this file as verified.
+
+pub const CTRL: u32 = 0x00;
+
+pub const STATUS: u32 = 0x04;
+
+pub const IRQ_EN: u32 = 0x08;
+
+pub const IRQ_STAT: u32 = 0x0C;
+
+pub const NUM_LAYERS: u32 = 0x10;
+
+pub const NEURONS: u32 = 0x14;
+
+pub const CHUNKS: u32 = 0x18;
+
+pub const THRESHOLD: u32 = 0x1C;
+
+pub const WEIGHT_ADDR_LO: u32 = 0x20;
+
+pub const WEIGHT_ADDR_HI: u32 = 0x24;
+
+pub const DMA_CTRL: u32 = 0x28;
+
+pub const DMA_STAT: u32 = 0x2C;
+
+pub const UNMAPPED_READ_VALUE: u32 = 0xDEADBEEF;
+
+pub const CTRL_START_BIT: u32 = 0;
+
+pub const CTRL_START_MASK: u32 = (1 << CTRL_START_BIT);
+
+pub const STATUS_BUSY_BIT: u32 = 0;
+
+pub const STATUS_DONE_BIT: u32 = 1;
+
+pub const STATUS_ERROR_BIT: u32 = 2;
+
+pub const STATUS_BUSY_MASK: u32 = (1 << STATUS_BUSY_BIT);
+
+pub const STATUS_DONE_MASK: u32 = (1 << STATUS_DONE_BIT);
+
+pub const STATUS_ERROR_MASK: u32 = (1 << STATUS_ERROR_BIT);
+
+pub const IRQ_INFERENCE_DONE_BIT: u32 = 0;
+
+pub const IRQ_DMA_DONE_BIT: u32 = 1;
+
+pub const IRQ_ERROR_BIT: u32 = 2;
+
+pub const IRQ_INFERENCE_DONE_MASK: u32 = (1 << IRQ_INFERENCE_DONE_BIT);
+
+pub const IRQ_DMA_DONE_MASK: u32 = (1 << IRQ_DMA_DONE_BIT);
+
+pub const IRQ_ERROR_MASK: u32 = (1 << IRQ_ERROR_BIT);
+
+pub const IRQ_ALL_MASK: u32 = ((IRQ_INFERENCE_DONE_MASK | IRQ_DMA_DONE_MASK) | IRQ_ERROR_MASK);
+
+pub const CSR_COUNT: usize = 12;
+
+pub const CSR_OFFSETS: [u32; CSR_COUNT as usize] = [CTRL, STATUS, IRQ_EN, IRQ_STAT, NUM_LAYERS, NEURONS, CHUNKS, THRESHOLD, WEIGHT_ADDR_LO, WEIGHT_ADDR_HI, DMA_CTRL, DMA_STAT];
+
+pub fn count_ones_u32(x: u32) -> u32 {
+    return count_ones_u64((x as u64));
+}
+
+pub fn count_ones_u64(x: u64) -> u32 {
+    let mut c: u32 = 0;
+    let mut y: u64 = x;
+    while (y != 0) {
+        c = (c + ((y & 1) as u32));
+        y = (y >> 1);
+    }
+    return c;
+}
+
+pub const B_UNDERSCORE: u8 = 95;
+
+pub fn alpha(c: u8) -> bool {
+    return (((c >= 65) && (c <= 90)) || ((c >= 97) && (c <= 122)));
+}
+
+pub fn digit(c: u8) -> bool {
+    return ((c >= 48) && (c <= 57));
+}
+
+pub fn same(s: &[u8], w: &'static str) -> bool {
+    if (s.len() != w.len()) {
+        return false;
+    }
+    let mut k: usize = 0;
+    while (k < w.len()) {
+        if (s[(k) as usize] != w.as_bytes()[(k) as usize]) {
+            return false;
+        }
+        k = (k + 1);
+    }
+    return true;
+}
+
+pub fn word(c: u8) -> bool {
+    return ((alpha(c) || digit(c)) || (c == B_UNDERSCORE));
+}
+

bootstrap/src/host/mod.rs

@@ -31,7 +31,7 @@ pub mod checksum;
 pub mod cmdq;
 pub mod config;
 pub mod configreg;
-pub mod csr_map;
+#[path = "../../gen/rust/host/csr_map.rs"] #[allow(dead_code, unused_parens, unused_mut, unused_variables, non_snake_case, unused_assignments, unexpected_cfgs, clippy::all)] pub mod csr_map; // specs/host/csr_map.t27, by `t27c gen-rust`
 pub mod descring;
 pub mod diag;
 pub mod dma;