gHashTag · Oct 20, 2026 · Oct 20, 2026 · Oct 20, 2026
@@ -1,21 +1,25 @@
 {
-  "built_by": "t27c-bootstrap@0.5.2+42a4860c4",
+  "built_by": "t27c-bootstrap@0.5.2+2d3203e90",
   "closure": [
     {
       "spec": "specs/analog/linear.t27",
       "spec_hash": "sha256:3ddef7be183aba583ed285334ee389b48a65b41335e98914514235db7c4e5d62"
     },
     {
       "spec": "specs/analog/mos_psp103.t27",
-      "spec_hash": "sha256:3edf0828e56e30977b96c2e943d203aac805fd197800d37a57fb4fc61c7152d8"
+      "spec_hash": "sha256:e04b69e5c43188a3d46a4c0949cfc727f239721de73fb46e92c8a845bbbbc98e"
     },
     {
       "spec": "specs/analog/mos_psp103_50c_data.t27",
       "spec_hash": "sha256:9e68629797a29516836ca3e0b5e4881b0e751d847c58fd52b63e8f69746dbbe1"
     },
     {
       "spec": "specs/analog/mos_psp103_data.t27",
-      "spec_hash": "sha256:d233143ed2fa30d3bd0ff9546a2df008d568e4a4d9c7e0ef69ffedee2e92a5d6"
+      "spec_hash": "sha256:86e7c154c88a325e41ff4a154a3b766cb8d65e89e2ea82176b46ee4fc523dd74"
+    },
+    {
+      "spec": "specs/analog/mos_psp103_gates.t27",
+      "spec_hash": "sha256:63ec92b62957ef68e8522c4dc392727ef8e5dc3b97195d519d68da1193b83e66"
     },
     {
       "spec": "specs/analog/sar_adc.t27",
@@ -51,23 +55,23 @@
     }
   ],
   "config": "gen=c,rust,verilog,zig;tests=zig",
-  "gen_hash_c": "sha256:7c9dd3964fa325d00333c76dc95779c578609de9eca69b4e73d0b3a4feb4c225",
-  "gen_hash_rust": "sha256:da5d89f055e1e0b42d261c493bc87dea4a4f0a089f1e3ab75b125675c43300cf",
-  "gen_hash_verilog": "sha256:a4a93c52656bc335637904b014d2b36d5e2a6f1ab7acfafeb29a4fc30e328080",
-  "gen_hash_zig": "sha256:f96ed14294d3b6b5456f01db4128d08c40f7dc921c9cb1760f53ace64b03a41d",
+  "gen_hash_c": "sha256:34ccbab9cc4e3487395ef4e9b572a107c27a6dcfc9f1fce65e25448c65d2460d",
+  "gen_hash_rust": "sha256:fb56af614562c17edf7ddf801463a2b0cab6650b4833e140e3d753d7b72fe2b8",
+  "gen_hash_verilog": "sha256:c2311f1cb2c8fd5da7cda29c7c498104e62920a3d1cf3e17bfa0fd85eefb514c",
+  "gen_hash_zig": "sha256:23badcb27fb8ab78bc62a2956cdc25171e5d9e3274c50afe622e16c92c931e43",
   "module": "AnalogAcceptSar",
   "ring": 12,
   "seal_schema": 2,
-  "sealed_at": "2026-10-20T03:11:58Z",
+  "sealed_at": "2026-10-20T08:13:43Z",
   "sealed_by": "t27c-bootstrap@0.5.2",
-  "spec_hash": "sha256:47df48dd24939e164d669ed536f0fc5c7feb03edba165e7c7238212ae1354ab1",
+  "spec_hash": "sha256:815322645790478d663c1b0a8ce688e419fa7f78e2d9718042e7695d110f6087",
   "spec_path": "specs/analog/accept_sar.t27",
   "tests": {
     "failed": 0,
     "failing": [],
     "forced": false,
-    "passed": 13,
-    "total": 13,
+    "passed": 14,
+    "total": 14,
     "vacuous": 0
   },
   "toolchain": {

@@ -0,0 +1,41 @@
+{
+  "built_by": "t27c-bootstrap@0.5.2+2d3203e90",
+  "closure": [
+    {
+      "spec": "specs/analog/mos_psp103.t27",
+      "spec_hash": "sha256:e04b69e5c43188a3d46a4c0949cfc727f239721de73fb46e92c8a845bbbbc98e"
+    },
+    {
+      "spec": "specs/analog/mos_psp103_data.t27",
+      "spec_hash": "sha256:86e7c154c88a325e41ff4a154a3b766cb8d65e89e2ea82176b46ee4fc523dd74"
+    },
+    {
+      "spec": "specs/analog/mos_table.t27",
+      "spec_hash": "sha256:54e248069ae620d18d260231e238b6bc42dc3c65792bd1673b162c2dc97b2edb"
+    }
+  ],
+  "config": "gen=c,rust,verilog,zig;tests=zig",
+  "gen_hash_c": "sha256:a27f3f394d8594134c3259e724858912d29f0870219ff3087c2beefaabb53a7f",
+  "gen_hash_rust": "sha256:773c19b0e5918f14274d5677437cec1ddca6bbba9a290593c7c74849913f0594",
+  "gen_hash_verilog": "sha256:e259d778dda4a1a118f8c81187e7dc22a319b098f3af0d00d7b46bb3b81b45a4",
+  "gen_hash_zig": "sha256:2ca337a6c0d2ccd3f92b1ad4e07d69298fc4d79b81075225c72f96f1829e1a0c",
+  "module": "AnalogMosPsp103Gates",
+  "ring": 12,
+  "seal_schema": 2,
+  "sealed_at": "2026-10-20T08:13:50Z",
+  "sealed_by": "t27c-bootstrap@0.5.2",
+  "spec_hash": "sha256:63ec92b62957ef68e8522c4dc392727ef8e5dc3b97195d519d68da1193b83e66",
+  "spec_path": "specs/analog/mos_psp103_gates.t27",
+  "tests": {
+    "failed": 0,
+    "failing": [],
+    "forced": false,
+    "passed": 6,
+    "total": 6,
+    "vacuous": 0
+  },
+  "toolchain": {
+    "test_runner": "sha256:8512b80da533b79289110fca4a65f3336abd7a059ca4b72ea595d5e33ff8ad10",
+    "zig": "0.16.0"
+  }
+}
@@ -0,0 +1,78 @@
+IHP SG13G2 two-input gates and the transmission gate off, DC: output levels and off leakage, corner mos_tt, 27 C
+* specs/analog/decks/accept_gates.cir -- reference data for specs/analog/mos_psp103_gates.t27 and its use in specs/analog/accept_sar.t27 (M5d, #11263, epic #10486).
+* A netlist plus a .control block that prints the numbers. The cells are the nand, the nor and the tgate of the golden SAR ADC netlist, with the W, L and m of their devices
+* (nmos 1.0 um / 0.45 um, pmos 3.0 um / 0.45 um, ng 1, m 1), which are facts of the circuit; none of its text is copied. The model is the IHP SG13G2 PSP103 of
+* IHP-Open-PDK 21133f21, section mos_tt, 27 C, the one of the tables in mos_psp103_data.t27. Paths are NOT in this file: ngspice reads IHP_PDK and IHP_OSDI from the environment.
+* Run: IHP_PDK=<checkout> IHP_OSDI=<osdi dir> ngspice -b accept_gates.cir    (ngspice-47)
+* What it prints (volts and amperes, 12 digits):
+*   dnd00 dnd01 dnd10 dnr00  the 1 levels as the droop under the supply, 1.5 V minus the output, of the nand for the inputs A B = 00, 01, 10 and of the nor for 00
+*   v(nd11) v(nr01) v(nr10) v(nr11)  the 0 levels, the output itself, of the nand for 11 and of the nor for 01, 10, 11
+*   The levels are the DC solution with no load, which is the level a gate settles to into 10 fF.
+*   i(vli1) i(vlo1)         the tgate off (pmos gate 1.5 V, nmos gate 0 V) with the input at 1.5 V and the output at 0 V: the current of the input source and of the output source (the
+*   i(vli2) i(vlo2)         same with the input at 0 V and the output at 1.5 V: the two roles exchanged, so the same two numbers); the two differ by 14 pA, the size of
+*                           a junction leakage, which sits in different terminals of the two sources; the terms are not separated here.
+* Solver options: reltol 1e-9, vntol 1e-12, abstol 1e-15, gmin 1e-18 (no leak is added by the simulator), itl1 500: the levels are microvolts and the leakage picoamperes. At gmin 1e-18
+* the operating point is reached by source stepping (ngspice says so in its log), which is the solver working, not a failure of the run.
+.lib $IHP_PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+.subckt nand2 a b vdd out vss
+XM1 n1 b vss vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+XM2 out a n1 vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+XM3 out a vdd vdd sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+XM4 out b vdd vdd sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+.ends
+.subckt nor2 a b vdd out vss
+XM1 out a vss vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+XM2 out b vss vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+XM3 out b n1 vdd sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+XM4 n1 a vdd vdd sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+.ends
+.subckt tgate clk nclk in out vdd vss
+XM1 out clk in vdd sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+XM2 in nclk out vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+.ends
+VDD vdd 0 1.5
+V0 l0 0 0
+V1 l1 0 1.5
+Xnd00 l0 l0 vdd nd00 0 nand2
+Xnd01 l0 l1 vdd nd01 0 nand2
+Xnd10 l1 l0 vdd nd10 0 nand2
+Xnd11 l1 l1 vdd nd11 0 nand2
+Xnr00 l0 l0 vdd nr00 0 nor2
+Xnr01 l0 l1 vdd nr01 0 nor2
+Xnr10 l1 l0 vdd nr10 0 nor2
+Xnr11 l1 l1 vdd nr11 0 nor2
+Cnd00 nd00 0 10f
+Cnd01 nd01 0 10f
+Cnd10 nd10 0 10f
+Cnd11 nd11 0 10f
+Cnr00 nr00 0 10f
+Cnr01 nr01 0 10f
+Cnr10 nr10 0 10f
+Cnr11 nr11 0 10f
+* the tgate off, full swing both ways
+VLI1 li1 0 1.5
+VLO1 lo1 0 0
+Xoff1 l1 l0 li1 lo1 vdd 0 tgate
+VLI2 li2 0 0
+VLO2 lo2 0 1.5
+Xoff2 l1 l0 li2 lo2 vdd 0 tgate
+.options temp=27 reltol=1e-9 vntol=1e-12 abstol=1e-15 gmin=1e-18 itl1=500
+.control
+pre_osdi $IHP_OSDI/psp103.osdi
+pre_osdi $IHP_OSDI/psp103_nqs.osdi
+set num_threads=2
+set numdgt=12
+op
+let dnd00 = 1.5 - v(nd00)
+let dnd01 = 1.5 - v(nd01)
+let dnd10 = 1.5 - v(nd10)
+let dnr00 = 1.5 - v(nr00)
+echo BEGIN gates
+print dnd00 dnd01 dnd10
+print v(nd11)
+print dnr00
+print v(nr01) v(nr10) v(nr11)
+print i(vli1) i(vlo1) i(vli2) i(vlo2)
+echo END gates
+.endc
+.end
@@ -0,0 +1,89 @@
+IHP SG13G2 PSP103 bootstrapped tracking switch, DC input held through one clock pulse: tracking error, hold step, droop, corner mos_tt, 27 C
+* specs/analog/decks/accept_switch.cir -- reference data for specs/analog/accept_sar.t27 (M5d, #11263, epic #10486). The tracking_switch cell of the golden SAR ADC netlist, ten
+* transistors with the W, L and m of its devices (nmos 1.0 um / 0.45 um, pmos 3.0 um / 0.45 um, ng 1, m 1 -- facts of the circuit, none of its text), the inverter that makes
+* the complement of the clock, the boost capacitor of 603.2 fF (cap_cmim 20 um x 20 um at the IHP PDK 21133f21: C = CJ L W + 2 CJSW (L + W), see sar_switch.t27) and the cell's seven
+* 4 fF node capacitors, on the PSP103 of the IHP SG13G2 PDK, section mos_tt, 27 C. specs/analog/sar_switch.t27 is the SAME cell with the SQUARE LAW (MOSFET level 1); here it is
+* the foundry's model, to see what the square law leaves out. Paths are NOT in this file: ngspice reads IHP_PDK and IHP_OSDI from the environment.
+* Run: IHP_PDK=<checkout> IHP_OSDI=<osdi dir> ngspice -b accept_switch.cir    (ngspice-47)
+* The run: the clock rises over 2 ns, stays at 1.5 V for 80 ns (the track phase) and falls over 2 ns; the period of the golden deck is 500 ns, so the hold lasts to 500 ns. Four copies of the
+* cell share the clock, each with its own input held at a constant: 0.3 V and 1.2 V into 2 pF (the conditions of the external team's report of 2026-10-16: te_b1, te_b2) and 0.2 V and
+* 1.3 V into 3930.2 fF (the conditions of sar_switch.t27: the DAC's top plate; te_a1, te_a2). The output load is the 4 fF of the cell plus the load named here. Each output starts 0.1 V under its input.
+* What it prints (.meas, 6 digits; the tracking error is read as a difference so that it keeps its digits):
+*   te_xx   V(out) - V(in) at 81.9 ns, the end of the track phase (the clock falls from 82 ns)
+*   vo_f_xx V(out) at 81.9 ns; vo_h_xx at 86 ns, two ns after the fall ends: the hold step is vo_h - vo_f; vo_e_xx at 104 ns: the 20 ns droop of sar_switch.t27 is vo_e - vo_h;
+*   vo_z_xx at 499 ns: the droop over the whole hold is vo_z - vo_h.
+* Solver options: reltol 1e-6, vntol 1e-9, abstol 1e-13, gmin 1e-18 (no leak is added by the simulator), a step of at most 100 ps.
+.lib $IHP_PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+.subckt inv vin vdd vss vout
+XMP vout vin vdd vdd sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+XMN vout vin vss vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+.ends
+.subckt trk vdd vss vin vout clks
+XM1 net1 clks vdd vdd sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+XM2 net1 clks net2 vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+XM3 net1 net3 net2 vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+XM4 net2 n_clks vss vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+XM5 vin net3 net2 vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+XM6 vout net3 vin vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+XM7 vdd net3 net4 net4 sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+XM8 net3 vdd net5 vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+XM9 net5 n_clks vss vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+XM10 net3 net1 net4 net4 sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+x1 clks vdd vss n_clks inv
+C3 net2 net4 603.2f
+C1 net4 0 4f
+C2 vout 0 4f
+C4 net1 0 4f
+C6 net3 0 4f
+C7 net5 0 4f
+C8 net3 0 4f
+C5 net2 0 4f
+.ends
+VDD vdd 0 1.5
+VCLK clks 0 PULSE(0 1.5 0 2n 2n 80n 500n)
+Via1 ina1 0 0.2
+Via2 ina2 0 1.3
+Vib1 inb1 0 0.3
+Vib2 inb2 0 1.2
+Xa1 vdd 0 ina1 outa1 clks trk
+Xa2 vdd 0 ina2 outa2 clks trk
+Xb1 vdd 0 inb1 outb1 clks trk
+Xb2 vdd 0 inb2 outb2 clks trk
+CLa1 outa1 0 3930.2f
+CLa2 outa2 0 3930.2f
+CLb1 outb1 0 2p
+CLb2 outb2 0 2p
+Bta1 tea1 0 V = v(outa1) - v(ina1)
+Bta2 tea2 0 V = v(outa2) - v(ina2)
+Btb1 teb1 0 V = v(outb1) - v(inb1)
+Btb2 teb2 0 V = v(outb2) - v(inb2)
+.ic v(outa1)=0.1 v(outa2)=1.2 v(outb1)=0.2 v(outb2)=1.1
+.options temp=27 reltol=1e-6 vntol=1e-9 abstol=1e-13 gmin=1e-18 itl4=500
+.tran 100p 500n 0 100p
+.meas tran te_a1 find v(tea1) at=81.9n
+.meas tran te_a2 find v(tea2) at=81.9n
+.meas tran te_b1 find v(teb1) at=81.9n
+.meas tran te_b2 find v(teb2) at=81.9n
+.meas tran vo_f_a1 find v(outa1) at=81.9n
+.meas tran vo_h_a1 find v(outa1) at=86n
+.meas tran vo_e_a1 find v(outa1) at=104n
+.meas tran vo_z_a1 find v(outa1) at=499n
+.meas tran vo_f_a2 find v(outa2) at=81.9n
+.meas tran vo_h_a2 find v(outa2) at=86n
+.meas tran vo_e_a2 find v(outa2) at=104n
+.meas tran vo_z_a2 find v(outa2) at=499n
+.meas tran vo_f_b1 find v(outb1) at=81.9n
+.meas tran vo_h_b1 find v(outb1) at=86n
+.meas tran vo_e_b1 find v(outb1) at=104n
+.meas tran vo_z_b1 find v(outb1) at=499n
+.meas tran vo_f_b2 find v(outb2) at=81.9n
+.meas tran vo_h_b2 find v(outb2) at=86n
+.meas tran vo_e_b2 find v(outb2) at=104n
+.meas tran vo_z_b2 find v(outb2) at=499n
+.control
+pre_osdi $IHP_OSDI/psp103.osdi
+pre_osdi $IHP_OSDI/psp103_nqs.osdi
+set num_threads=2
+run
+.endc
+.end
@@ -0,0 +1,44 @@
+IHP SG13G2 transmission gate conducting, DC: resistance over the output level, corner mos_tt, 27 C
+* specs/analog/decks/accept_tgate.cir -- reference data for specs/analog/mos_psp103_gates.t27 and its use in specs/analog/accept_sar.t27 (M5d, #11263, epic #10486).
+* The tgate of the golden SAR ADC netlist (a pmos 3.0 um / 0.45 um with its bulk on the supply, an nmos 1.0 um / 0.45 um with its bulk on ground; ng 1, m 1 -- facts of the circuit,
+* none of its text) conducting: pmos gate 0 V, nmos gate 1.5 V. The input is held 10 mV above the output through a behavioural source whose branch current is the tgate's
+* current, the output is swept from 0.10 V to 1.40 V in steps of 50 mV (27 points), and R = 10 mV / I, the measurement of sar_off_ron.cir at 27 C. Model: IHP SG13G2 PSP103 of
+* IHP-Open-PDK 21133f21, section mos_tt. Paths are NOT in this file: ngspice reads IHP_PDK and IHP_OSDI from the environment.
+* Run: IHP_PDK=<checkout> IHP_OSDI=<osdi dir> ngspice -b accept_tgate.cir    (ngspice-47)
+* What it prints (ohm, 12 digits), between BEGIN and END:
+*   rtg     the real cell: the nmos source is the output, its bulk is on ground, so its source-to-bulk voltage is the output level; the pmos source is the input, its bulk on the supply,
+*           so its source-to-bulk voltage is 1.5 V minus the input. The BODY EFFECT is in it.
+*   rnb     the same two devices with each bulk tied to its own source (the nmos bulk to the output, the pmos bulk to the input): the condition the current tables of
+*           mos_psp103_data.t27 were made under (source and bulk on the same rail), so what the table model should reproduce if the body effect is what separates it from rtg.
+* Solver options: reltol 1e-9, vntol 1e-12, abstol 1e-15; the simulator's default gmin (1e-12 S: 1e-7 of a 7 uA current), itl1 500.
+.lib $IHP_PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib mos_tt
+.subckt tgate clk nclk in out vdd vss
+XM1 out clk in vdd sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+XM2 in nclk out vss sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+.ends
+.subckt tgate_nb clk nclk in out
+XM1 out clk in in sg13_lv_pmos w=3.0u l=0.45u ng=1 m=1
+XM2 in nclk out out sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
+.ends
+VDD vdd 0 1.5
+V0 l0 0 0
+V1 l1 0 1.5
+VOUT tout 0 0.1
+BIN tin 0 V = v(tout) + 0.01
+Xon l0 l1 tin tout vdd 0 tgate
+BIN2 tin2 0 V = v(tout) + 0.01
+Xnb l0 l1 tin2 tout tgate_nb
+.options temp=27 reltol=1e-9 vntol=1e-12 abstol=1e-15 itl1=500
+.control
+pre_osdi $IHP_OSDI/psp103.osdi
+pre_osdi $IHP_OSDI/psp103_nqs.osdi
+set num_threads=2
+set numdgt=12
+dc vout 0.1 1.4 0.05
+let rtg = 0.01 / abs(i(bin))
+let rnb = 0.01 / abs(i(bin2))
+echo BEGIN ron
+print rtg rnb
+echo END ron
+.endc
+.end