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ci(dupe): turn duplicate-bodies green -- share gen_w tree helpers, record STEP copies (Closes #9633) - #9970
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(cherry picked from commit f9945cbfa7890196c9406dc359f836e6ea13bcdb)
tools/dupe_scan.py --bless on the Railway lab. The diff is exactly the STEP groups: bit_at, build_report_frame, debug_state_bits, led_counter_next, led_state_next, uart_tx_bit_at and weight_sign at 2, on_comb 3,2 -> 3,2,2. Nothing else moved. They stay copied until gen-verilog emits functions brought in by use (#8769). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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October 17, 2026 14:50
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Closes #9633. Refs #9631, #8769. Supersedes draft #9636; its two commits are carried here unchanged, with authorship preserved.
Why
duplicate-bodieshas been red on every master push since about 2026-10-15, and every open PR inherits it. The gate lists 12 groups that recentspecs/port/**ports introduced. They split into two families, and each family gets a different fix.gen_w family: real dedupe (flat_index, is_ascii, indent, build_level)
specs/port/scripts/gen_w_tree.t27(new, from spec(port): share tree helpers across eight gen_w ports (Closes #9633) #9636) holds the tree helpers once. The eight portsgen_w698/709/713/716/721/728/729/732useit, in the same way gen_w310..322 usegen_w_blocks.t27on master.flat_index 2andis_ascii 2are removed because those groups are gone.docs/reports/suite_expectations.json: the gen_w698 gen-verilog entry is retired (83 -> 82). The corpus ratchet reported it as an unexpected pass after theindentstring table moved out.useis called but never defined, and gen-verilog exits 0 #8769: none of these script ports declareson_comboron_clock, so their gen-verilog output has no data port and is not a hardware artefact. That is the same trade the mergedgen_w_blocksprecedent accepted.STEP1/STEP2 family: recorded on purpose (8 groups)
weight_sign, led_state_next, led_counter_next, debug_state_bits, bit_at, uart_tx_bit_at, build_report_frame and on_comb.
In
trinity_block_step{1,2}_top.t27,on_combis the module's data port: gen-verilog emitsassign result = on_comb(...), and the body calls led_pin, led_state_next, debug_state_bits and tx_ready. gen-verilog does not emit a function brought in byuse(#8769, open). A shared module would therefore leave both tops' RTL calling functions it never defines, and gen-verilog would still exit 0. #8769 itself names copying as the only workaround. Both specs now say this in their header. The ledger records the copies, and #9631 stays open to share them once #8769 is fixed.The bless was run with
tools/dupe_scan.py --blesson the Railway lab, and the full ledger diff was inspected. The diff is exactly these 8 groups: seven new2lines, pluson_comb 3,2 -> 3,2,2. No other line moved.Checks (Railway lab, release t27c built at this base)
python3 tools/dupe_scan.py --self-test: ok, 11 shapes.python3 tools/dupe_scan.py:ok: no new duplicate body, and none of the known groups grew.(722 of 10495 bodies, 217 groups). On master the same command fails with the 12 errors.t27c parseexits 0 for all 11 touched specs.t27c test-reportexits 0 with 0 vacuous for every touched spec: gen_w_tree 7/7, each gen_w port 13/13, step1 17/17, step2 19/19.python3 tools/check_duplicate_declarations.pyexits 0.Only
.t27is written by hand; the ledger and expectation are tool or data files. No seal is touched, because none of these specs is sealed.🤖 Generated with Claude Code