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spec(port): share tree helpers across eight gen_w ports (Closes #9633) - #9636
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This was referenced Oct 15, 2026
…g#9633) (cherry picked from commit f9945cbfa7890196c9406dc359f836e6ea13bcdb)
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Critical review finding on this PR: do not merge, even with green checks. gen-verilog loses the moved helper functions (#8769). Evidence, same base t27c, no code changed:
What this changes:
Status: not mergeable and not CI green. The PR stays draft. Dependencies as listed in the body: #8769 (blocker), #9631, #9632, #9634, #9600. No new request to the owner is made by this comment. Dmitrii Fedorov (@dmitrii-f-t27) |
This was referenced Oct 15, 2026
gen-verilog: a function brought in by
use is called but never defined, and gen-verilog exits 0
#8769
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policy: owner-approved-foreign only for new foreign files and the gate itself (Closes #10197)
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Closes #9633.
Draft. BLOCKED, not mergeable even with every check green: gen-verilog drops the helper functions that moved behind
use(#8769). See "Blocked" below. This PR depends on the shared base listed under Dependencies.What
Eleven paths change. The first commit, 3518b72, has exactly ten of them (264 insertions, 1094 deletions; historical figures). A later commit adds the eleventh, a data file (below).
TreeBuild,indent,elem_x,elem_y,build_level,build_tree,flat_indexandis_ascii, written once, with 7 tests.use port::scripts::gen_w_tree;is added. Header constants,generate()and every test are unchanged.flat_index 2,is_ascii 2). Nothing is raised.max_entriesgoes from 83 to 82. No other entry, cap or expiry changes, and no broad bless was run.This is a conditional candidate, not a proven improvement (see below).
What was observed about the expectation
The corpus ratchet of the first commit failed (run 38764724462, job 116524835401): ledger 83 of 83, UNEXPECTED FAILURES 0, UNEXPECTED PASSES 1: specs/port/scripts/gen_w698.t27 [gen-verilog], "fixed -- remove from ledger".
gen_w698 had spelled
indentas a table, an array of strings (W469, #1959); that table is gone. It was an observed unexpected pass with a critical unresolved dependency, not a demonstrated fix: see Blocked. With the entry removed the suite ratchetis clean locally (UNEXPECTED FAIL 0, UNEXPECTED PASS 0), but that check does not detect lost helper definitions, so a clean result does not prove the code is preserved.
Blocked: #8769
gen-verilog imports enum and struct types through
usebut not functions. Same base t27c, two outputs: the gen-verilog of the unchanged gen_w709 definesfunction indent,elem_x,elem_y,build_level,build_treeand more (/tmp/t27-ci-gen-w709-base.v);the gen-verilog of gen_w698 after its helpers moved behind
usedefines onlyfunction generate, and its test names are only comments (/tmp/t27-ci-gen-w698-after.v). The Zig and Rust targets andt27c test-reportpass, but the Verilog output loses code.Exit code 0 does not prove preservation. This PR must not merge until #8769 is fixed and the helper definitions are present in the generated Verilog; the expectation removal is justified only after that. The root issue is #8769.
Same pattern as specs/port/scripts/gen_w_blocks.t27 for gen_w310..gen_w322. No Rust, no workflow, no generated file, no seal, no exception entry, no file of #9622 or #9630 is touched.
Checks run on this commit
t27b: 7 of 7, 33 asserts (/tmp/t27-ci-tree-tests.log, /tmp/t27-ci-tree-native.log).blocked ConstDecl, exactly as in the master artifact. This PR does not claim they are native green.What this PR does and does not turn green
build_level,indent,flat_indexandis_asciiviolations frompython3 tools/dupe_scan.py.Dependencies
PRs #9622 and #9630 stay red until these are integrated; this PR alone does not make them green.
Dmitrii Fedorov (@dmitrii-f-t27)