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…flows 5b09159 (2026-08-02) moved the node logic into fpga/portable/trinet_node_core.v. The fleet and portability workflows were given the new file; ax7203-trinet-baud.yml and ax7203-trinet-node-v2.yml were not, and both have been red on main since 2026-08-02. Neither runs on pull_request, so no PR showed it. - node-v2 golden: iverilog "Unknown module type: trinet_node_core" (exit 3), bitstream skipped. - baud: Yosys printed the ERROR but the step stayed green (tee without pipefail, and the next grep matched the ERROR line). The job then built the chipdb and ran 16 nextpnr attempts on a missing node.json, and failed as "no clean seed across heap+sa x8". Add the core to both workflows' source lists and paths filters, and set pipefail on the six steps that pipe into tee, so a Yosys error stops at Yosys. Their six tee_pipefail_baseline entries are removed (78 -> 72). Local controls, sources from origin/main 57de4a1: - iverilog without the core: exit 3, CI's error; with it: vvp prints "SIM RESULT: 6/6 keyed receipts bit-exact (fails=0)", TB PASS. - yosys hierarchy -check (Xilinx cell libs): exit 1 without the core, exit 0 with it. - tools/check_tee_pipefail.py: 72 known, 0 new, exit 0; removing the Yosys step's marker makes it flag the step. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Summary by t27-beesThis PR fixes two TRI-NET CI workflows to include Worth a look
Read: 3 files, +15 -9, the whole diff. Head |
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Fixes #888. Part of #851 (W15).
Change
ax7203-trinet-baud.ymlandax7203-trinet-node-v2.ymlnow readfpga/portable/trinet_node_core.vin everyread_verilog/iveriloglist, and name it inpaths:. 5b09159 moved the node logic there on 2026-08-02.ax7203-trinet-fleet.ymlandtrinet-portability.ymlalready read it.set -o pipefailon the six steps that pipe intotee. A Yosys error now fails the Yosys step instead of surfacing 16 nextpnr attempts later asno clean seed across heap+sa x8. The Yosys and fasm2bit steps carry a# tee-pipefail:marker, because the gate takes-nocarryanddocker … bash -cfor a shell of their own.tools/tee_pipefail_baseline.txt: the six entries are removed, 78 → 72. The gate is a ratchet, and a stale entry fails it.Measured
Locally, sources from
origin/main57de4a1:iverilog -g2012, Node v2 golden TBUnknown module type: trinet_node_core(the error in CI run 30796536505)vvpSIM RESULT: 6/6 keyed receipts bit-exact (fails=0),TB PASSyosyshierarchy -check -top trinet_node_v2_ax7203with the Xilinx cell librariestools/check_tee_pipefail.pyCI: both workflows have no
pull_requesttrigger, so they were dispatched on this branch at e2756f9. Both passed (2026-10-05):golden: SipHashTB PASS;SIM RESULT: 6/6 keyed receipts bit-exact (fails=0),TB PASS.bitstream: Yosys 1489 LCs, routed with heap/1,.bitsha25677b5bfa9…0948e.bitbda1ef35…83ce. baud60: 1525 LCs, heap/1,6d2a8715…a429. baud120: 1545 LCs, heap/1,6fdf7192…8532Main's last runs of these two workflows (37225332354, 37225332379) failed at
iverilogand after 16 nextpnr attempts respectively.This PR's
doc-refsandorphan-artefactschecks are red for the same files asmainsince #510 merged (research/arxiv_gft/*,research/GFT_DEFECTS_2026-08-08.md,research/GF_INVENTORY_2026-08-08.md). It inherits them frommainand does not touch them. #872 fixes them.Not measured
--timing-allow-failand keep its log in/tmp, so a routed bitstream says nothing about timing.Cache not found for input keys: chipdb-xc7a200tfbg484-2-regymm-…), and each job built the chipdb. There was no chipdb entry onmainto restore: see ci: setup-zig caches fill the 10 GB Actions cache and evict every chipdb #844.🤖 Generated with Claude Code