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Fix assembly/disassembly for various VFPU opcodes - #22083
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Update armips for VFPU instruction parsing changes (Kingcom/armips#257) - fix transposed matrix register encodings (e.g. `vmidt.p E220` was assembling to `vmidt.p E202`) - fix immediate size for `vwbn.s` (is 8 bits, was limited to 5 bits) - fix `vd` register size for `vsocp.s/p` - fix `vhtfm2.p` and `vhtfm3.t` encoding - add missing instruction `vhtfm4.q` Fix `v(h)tfmX` disassembly (handle irregular vector size encoding) Fix `vsocp.s/p` disassembly (`vd` is double the size of `vs`)
hrydgard
approved these changes
Aug 11, 2026
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Update armips for VFPU instruction parsing changes (Kingcom/armips#257)
vmidt.p E220was assembling tovmidt.p E202)vwbn.s(is 8 bits, was limited to 5 bits)vdregister size forvsocp.s/pvhtfm2.pandvhtfm3.tencodingvhtfm4.qFix
v(h)tfmXdisassembly (handle irregular vector size encoding)Fix
vsocp.s/pdisassembly (vdis double the size ofvs)Identified & verified these changes by running the VFPU binaries pspautotests through a websocket API script asserting
assemble(op) == assemble(disassemble(op)).