Fix duplicate timer channels on FURYF4OSD and WARPF7

[sensei-hacker]

Summary

Two targets declare the same (timer, channel) on two different pins. Both pins are then muxed to one compare register, so they can only ever emit the same waveform — the second pad is not an independent output for any protocol, DSHOT or otherwise, and at higher motor counts the two entries fight over the same CCR.

A sweep of all 249 targets found these were the only two affected. After this PR that bucket is empty.

Changes

FURYF4OSD — PB10/PB11 removed

TIM2_CH3 was declared on both PA2 (S4_OUT) and PB10; TIM2_CH4 on both PA3 (S1_OUT) and PB11.

Per the STM32F405 datasheet AF table, PB10's only timer function is TIM2_CH3 (AF1) and PB11's only timer function is TIM2_CH4 (AF1) — there is no free channel to remap them to, so the two TIM_USE_ANY entries are removed. Both pads are this board's UART3 TX/RX. MAX_PWM_OUTPUT_PORTS drops 6 → 4 to match the outputs that remain.

User-visible: FURYF4OSD advertises 4 outputs instead of 6. Outputs 5 and 6 never worked as independent outputs, so nothing that previously functioned is lost.

WARPF7 — S6 moved to TIM8_CH3

TIM3_CH3 was declared on both PB0 (S1) and PC8 (S6), so S6 could only mirror S1. PC8 also reaches TIM8_CH3, which no other output on this board uses (DEF_TIM_AF__PC8__TCH_TIM8_CH3 already exists in timer_def_stm32f7xx.h), so S6 moves there. The board keeps all eight documented outputs.

Also in this file: S4 (PB11, TIM2_CH4) moves to its second DMA option, DMA1 Stream6. Its default Stream7 is the only stream TIM3_CH3 can use, so S1 claimed it first and S4 silently died at four motors. #11803 makes this same change on maintenance-10.x; release/9.1 does not have it.

Testing

• Both targets build clean, no warnings (FURYF4OSD 68.1% flash / 84.6% RAM; WARPF7 94.3% FLASH1).
• Role/DMA resolution simulated against a port of pwm_mapping.c's algorithm across motor counts 1–8: WARPF7 is now hazard-free at every count; FURYF4OSD reports no remaining duplicate or motor-vs-motor collision.
• Every DEF_TIM in both files re-validated against the STM32F405/F722 datasheet AF tables.
• Not tested on hardware — I have neither board. Confirmation from a FURYF4OSD or WARPF7 owner that motors still map correctly would be valuable before merge.

Notes

Pre-existing and not addressed here: FURYF4OSD's S3_OUT (TIM3_CH4, DMA1 Stream2) and LED strip (TIM5_CH1, DMA1 Stream2) share a stream, so the LED strip does not light when S3 uses DSHOT. Each channel has exactly one DMA option and PA0 has no other usable timer, so it cannot be fixed by remapping. Documented in #11803.

This PR touches lines that #11803 annotates with comments; whichever merges second will need a trivial comment-level conflict resolution.

[qodo-code-review]

ⓘ Qodo reviews are paused because the subscription is no longer active. Ask your workspace admin to reactivate the subscription to resume reviews. Manage billing

[qodo-free-for-open-source-projects]

PR Summary by Qodo

Fix duplicate timer channels on FURYF4OSD and WARPF7

🐞 Bug fix ⚙️ Configuration changes 🕐 20-40 Minutes

AI Description

• Remove FURYF4OSD timer aliases that cannot provide independent outputs.
• Remap WARPF7 S6 to an unused timer channel.
• Move WARPF7 S4 to a non-conflicting DMA stream.

Diagram

graph TD
    ROOT["Target Timer Maps"] --> FURY["FURYF4OSD"] --> FOUT["Four PWM Outputs"]
    ROOT --> WARP["WARPF7"] --> S6["S6 TIM8 CH3"]
    WARP --> S4["S4 TIM2 CH4"] --> DMA["DMA1 Stream6"]
    FURY --> UART["UART3 Pads Excluded"]

Loading

High-Level Assessment

The PR uses the appropriate target-specific fixes: remove FURYF4OSD aliases because PB10/PB11 have no unique timer channels, while preserving WARPF7's output count through PC8's available TIM8_CH3 mapping. Selecting S4's alternate DMA stream also resolves the independent stream collision without changing its pin or timer channel. Retaining mirrored aliases or reducing WARPF7's output count would provide no benefit.

Files changed (3) +6 / -6

Bug fix (2) +5 / -5

target.cRemove duplicate PB10 and PB11 timer outputs +2/-2

Remove duplicate PB10 and PB11 timer outputs

• Removes PB10/TIM2_CH3 and PB11/TIM2_CH4 output entries because they share compare registers with existing S4 and S1 outputs. Comments document why the UART3 pads cannot serve as independent timer outputs.

src/main/target/FURYF4OSD/target.c

target.cResolve S6 timer and S4 DMA collisions +3/-3

Resolve S6 timer and S4 DMA collisions

• Moves S6 from duplicate TIM3_CH3 to unused TIM8_CH3, preserving all eight outputs. Selects DMA variant 1 for S4, assigning DMA1 Stream6 instead of the Stream7 required by S1.

src/main/target/WARPF7/target.c

Other (1) +1 / -1

target.hAdvertise four valid PWM outputs +1/-1

Advertise four valid PWM outputs

• Reduces MAX_PWM_OUTPUT_PORTS from six to four so the target reports only independently usable outputs.

src/main/target/FURYF4OSD/target.h

[qodo-free-for-open-source-projects]

Code Review by Qodo

🐞 Bugs (0) 📘 Rule violations (0) 📎 Requirement gaps (0)

Great, no issues found!

Qodo reviewed your code and found no material issues that require review

Tip of the day

💡 Did you know, you can tweak Display preferences with a live preview to see your comment before it ships

More tips ↗ | Customize Qodo ↗ | Qodo docs ↗

[github-actions]

RAM / Flash usage vs. base commit c26316e — commit 4d2e5e5

Target	Flash Δ	RAM Δ
MATEKF405	±0 B (±0.00%)	±0 B (±0.00%)
MATEKF722	±0 B (±0.00%)	±0 B (±0.00%)
MATEKF765	±0 B (±0.00%)	±0 B (±0.00%)
MATEKH743	±0 B (±0.00%)	±0 B (±0.00%)

See RAM/flash optimization guide for techniques to reduce usage.

[github-actions]

Test firmware build ready — commit 4d2e5e5

Download firmware for PR #11874

245 targets built. Find your board's .hex file by name on that page (e.g. MATEKF405SE.hex). Files are individually downloadable — no GitHub login required.

Development build for testing only. Use Full Chip Erase when flashing.