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fpga(build): skip t27b bitstream specs in fpga-build -- fpga-lint and the elab ratchet green again (Closes #10300) - #10302

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fpga(build): skip t27b bitstream specs in fpga-build -- fpga-lint and the elab ratchet green again (Closes #10300)#10302
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Closes #10300

fpga-lint and the elaboration ratchet name two modules, rc_filter_ax7203 and ddr3_head_bandwidth, because both are written in t27b's bitstream idiom (pin attributes const x_LOC : str, empty-bodied primitive fns such as IBUFDS, PLLE2_ADV, litedram_core) and the gen-verilog command of t27c has no lowering for it. The decision and the reasons (skip, not a second lowering) are on #10300.

  • The fpga-build command of t27c prints SKIP <name>.v (t27b bitstream spec; ...) and generates nothing for a spec with a _LOC pin attribute. No spec or seal changes.
  • The two identical yosys script blocks in run_fpga_build are folded into one, so the file ends with fewer hand-written Rust lines than it started with (the foreign-budget gate allows no growth).
  • tools/elab_baseline.txt: drops the rc_filter_ax7203 8 row that fpga(ax7203): rc_filter without Verilog real -- f64 references in the tests, comptime_float PLL params (Closes #10294) #10296 added as a KNOWN GAP (a GONE row would fail the ratchet), and adds none for ddr3; the notes say why.

Measured on the Railway lab (t27c built from this branch):

  • fpga-build --smoke: 2 SKIP lines, 53 modules + wrapper.
  • CI yosys loop (read_verilog -sv -DSIMULATION; hierarchy -top): 54 pass, 0 fail (before: 54 pass, 2 fail).
  • tools/check_elab_ratchet.py: 206 errors, baseline 206, exit 0 (before: 278 vs 214, two NEW).
  • fpga-build --docker false --synth-only (the refactored path): synth.json written, exit 0. synth-readiness: READY.

Not covered: the t27c-generated Verilog of the two skipped specs is no longer linted. It was never the shipped RTL; that is t27b verilog output, covered by the board receipt (rc_filter 2130/2130 PASS). Linting t27b verilog output in CI is the follow-up once it runs there.

🤖 Generated with Claude Code

@gHashTag @claude
fpga(build): fpga-build skips t27b bitstream specs; no gen-verilog ro…
18c0384 
…ws for rc_filter_ax7203 and ddr3_head_bandwidth (Closes #10300)

Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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gHashTag force-pushed the fix/gen-verilog-bitstream-10300 branch from 873d9b3 to 18c0384 Compare October 18, 2026 08:04
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gHashTag enabled auto-merge (squash) October 18, 2026 08:04
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Generated at: 2026-10-18 08:05:39 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 50
PRs with All Checks Green 0
READY 0
FAILING 50
PENDING 0
NO CHECKS YET 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=0f8c66b9ed0e != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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gHashTag merged commit 30b4363 into master Oct 18, 2026
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gHashTag added a commit that referenced this pull request Oct 18, 2026
@gHashTag @claude
fpga(ax7203): rc_filter PLL params back to f64 so t27b passes the spe…
97bb27f 
…c again (Closes #10313) (#10314)

master's t27b-native-ratchet reads `specs/fpga/rc_filter_ax7203.t27:
ledger pass, now blocked: type comptime_float`. #10278 ledgered the spec
as t27b pass; #10296 then typed PLLE2_ADV's CLKIN1_PERIOD and
REF_JITTER1 as comptime_float so t27c gen-verilog would not emit
`input real`, and t27b rejects a comptime_float parameter. #10302 made
gen-verilog skip t27b bitstream specs, so that reason is gone: the two
parameters go back to f64 and the doc comment says why.

Measured on the Railway lab at master 9da2c5f, t27b and t27c built
there:
- t27b on master's spec: "unsupported construct type comptime_float at
  line 247"; on this spec: accepted, and `t27b build --elf` writes the
  object (the x86 lab has no t27b JIT; CI's arm64 runs the tests).
- `t27b verilog`: same 608 lines as master's; only the five
  `// ... (line N)` comments move by 2. The PLL instance still reads
  CLKIN1_PERIOD(5.0), REF_JITTER1(0.01), so the board RTL does not
  change.
- reference (t27c test-report, zig 0.16.0): 10 of 10 pass, 0 vacuous.
- seal regenerated with `t27c seal --save`: spec_hash 8fba8a41.

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
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fpga(build): skip t27b-only bitstream specs in fpga-build, not teach gen-verilog a second lowering (rc_filter_ax7203, ddr3_head_bandwidth)

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