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analog M4d-b: the delay cell remembers its last edge -- repeated clkc falls within 1.8 % of ngspice PSP103, CK edges within 1 % (Closes #10848) - #10898
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… falls within 1.8 % of ngspice PSP103, CK edges within 1 % (Closes #10848) The gate-level SAR logic of M4d had a stateless delay cell: a table of settled delays. In the self-timed loop nothing settles, and the repeated clkc falls came 13.2 ns after Valid against ngspice's 7.0 ns (83 to 90 % late). - The state of the nor3 output n1 and of the delay cell output n2 is their AGE, the time since each last crossed the other way. Four tables of age against delay (SL_HIST, 11 measured points each) from 21 calibration chains of the new specs/analog/decks/sar_delay_hist.cir scale the settled delays of the nor3 fall and rise and of the delay cell rise and fall; the age is ms[SL_TCH + g]. - Held-out check: 7 pulse trains (other spacings, none in the tables) are reproduced at every fall and rise within 5.1 %, the settled ones within 1.7 %. - Negative control: ms[SL_HON] = 0 (the stateless cell) fails the repeated-fall check by 83 to 90 % (180 % at the 15 / 15 ns pace). - Last fall with CK1 up as well: SL_C2_PM, fitted at one point. - Inverter after the delay cell: ngspice's delay for a slow edge (SL_IV_R/F). - CK edges (were 17 % early): the fight of the skew window (a node that held the weak value stays until the weak driver lets go) and the tgate In terminal load (SL_TG_IN_LOAD, fitted); CK11 .. CK2 within 1 %, CK1 3 % late. - SL_REPEAT_F_BOUND_PM = 1300 and SL_REPEAT_R_BOUND_PM removed; every clkc edge is held to SL_CLKC_BOUND_PM = 8 %. - The SAR_GOLDEN_SUBCKTS extraction line in the header and two decks dropped every `.ends`; fixed. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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Closes #10848
Follow-up of M4d (#10754, PR #10845). The gate-level SAR logic had a stateless delay cell (a table of settled delays); in the self-timed loop nothing settles, and its repeated clkc falls came 13.2 ns after Valid against ngspice's 7.0 ns. This PR gives the delay cell a state. All numbers below are from
t27c test-report specs/analog/sar_logic.t27and ngspice-47 + PSP103 (mos_tt, 50 C) runs of the committed decks.The state model
The state of an output is its AGE: the time since it last crossed the other way (the nodes are first-order, so their voltage is a function of that time). In ngspice every edge's delay is a single-valued curve of the age (sar_delay_hist.cir, 29 pulse-train chains). The model keeps
ms[SL_TCH + g], the time gate g's output last went from one known value to the other (out of the unknown start: a long rest), and scales the settled delay of an edge by a table of that age:SL_H_N1FSL_H_N2RSL_H_N1RSL_H_N2FEach table is 11 MEASURED points (linear between, flat outside), read from the fourth pulse of the 21 calibration chains (Wh = 30 ns with Wl = 16 .. 120 ns; Wl = 30 ns with Wh = 14 .. 120 ns). They are not fitted constants. Code 000 only; other codes scale it by their settled delay (not checked).
Numbers that ARE fitted or taken from a deck, with their source:
SL_TG_IN_LOAD = 0.43inverter inputs (was 0.15): FITTED to the CK11 .. CK2 delay; one number, so those ten edges are not an independent check of it.SL_C2_PM = 806: delay cell rise with two nor3 inputs high (Valid and CK1 on the last pulse), 4905 ps over the table's 6083 ps at that age, chain k01 of sar_delay_hist.cir. FITTED at one point.SL_IV_R(626, 466, 466, 436, 466, 436, 436, 657 ps by trim code) andSL_IV_F = 114: the inverter after the delay cell sees a slow edge; MEASURED asiv_<code>_r/fin sar_delay_cell.cir.Repeated clkc edges at the golden pace (sar_logic_ref.cir, SAR_logic + clock_gen, 11 Valid pulses), model against ngspice
SL_REPEAT_F_BOUND_PM = 1300andSL_REPEAT_R_BOUND_PMare removed. Every one of the 22 clkc edges is held toSL_CLKC_BOUND_PM = 80(8 %); the issue asked for 15 %.Held-out check
Seven pulse trains (sar_delay_hist.cir h01 .. h07: Wh / Wl = 20.2 / 19.8, 15 / 15, 25 / 25, 18 / 22, 24 / 16, 30 / 20, 22 / 38 ns, six pulses each) were not used for any table entry. Every one of their 42 falls and 42 rises is within the 8 % bound: worst 5.1 % (a fall, the second pulse of 15 / 15), the settled falls within 1.7 %, the settled rises within 0.4 %. The 21 calibration chains, whose points are in the tables, are reproduced within 0.9 % (falls) and 0.4 % (rises) at the fourth pulse, and not exactly (bound 3 %).
CK edge error (FR-002)
Explanation: the keeper's NMOS still pushes a weak 1 while the slave's NMOS pulls net3 down, so ngspice's net3 falls 28 ps after nCLK (133 ps after Valid), not 83 ps (the tgate arc alone). The remaining 41 ps is the tgate In terminal, which no arc deck measures: 0.15 inverter inputs was a guess, 0.43 reproduces ngspice. What is not explained: why the real terminal is 0.43 (4 um of diffusion, measured by nothing here), and the input-slope term is still absent. A CK FALLING (the swapped-pins control only) is still 20 % early (426 against 535 ps), unchanged.
SL_CK_BOUND_PM200 -> 50 permille,SL_CK_ABS_PS100 -> 30.Negative control
With the history switched off (
ms[SL_HON] = 0, the stateless cell of M4d) the golden pace's repeated falls are 83 .. 90 % late (828 .. 895 permille) and fail the check the remembering cell passes, and the 15 / 15 ns pace is 181 % off (assert innegative_control_the_stateless_delay_cell_fails_the_repeated_fall_check_that_the_remembering_one_passes).Other
SAR_GOLDEN_SUBCKTSextraction line in the spec header and in sar_logic_ref.cir / sar_gate_arcs.cir (grep -v -E '^.(end|global)') dropped every.endstoo; ngspice stopped at "Mismatch of .subckt ... .ends". Fixed to'^\.(end|global)([[:space:]]|$)'(verified identical to the file the decks need).option kluandset num_threads=8: 3 m 38 s for the 29 chains.msgrew from 5000 to 5500 slots (SL_TCH, SL_CELL, SL_FED, SL_HON); no other spec imports sar_logic.Gates
t27c test-report specs/analog/sar_logic.t27: tests 17, pass 17, FAIL 0, vacuous passes 0 of 17 (t27b: 17 passed, 0 failed).t27c seal --savethen--verify: all hashes MATCH; no other seal imports sar_logic.python3 -I tools/dupe_scan.py: no new duplicate body, none of the known groups grew.tri types ratchet: RATCHET: CLEAN.Not covered
Trim codes other than 000 (the history of 000 is scaled), ages below the calibrated range (Wh < 14 ns, Wl < 16 ns; a scratch prototype of the same law was 17 % off on the first rise of a 12 / 28 ns train), the closed loop through the comparator (M4e), other corners. Model speed against ngspice is not claimed.
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