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gen-verilog: do not wrap an assignment target in $signed -- fixes the systolic fpga-lint / fpga-conformance reds (Closes #10780) - #11094

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gen-verilog: do not wrap an assignment target in $signed -- fixes the systolic fpga-lint / fpga-conformance reds (Closes #10780)#11094
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fix/gen-verilog-signed-lvalue-10780

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@gHashTag gHashTag commented Oct 19, 2026

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Closes #10780

What

t27c gen-verilog wrote a signed packed array element on the left of an assignment as $signed(c[...]) = .... That is not a legal Verilog assignment target (yosys: unexpected TOK_TO_SIGNED; iverilog: syntax error). specs/fpga/systolic.t27 (#7719) hit it, and that is what has kept fpga-lint (read_verilog + hierarchy) (1/60 modules failed) and fpga-conformance (NEW systolic: 2 errors) red on master and on every pull request that touches cli/ or bootstrap/. #8844 did not cause it: the same error appears with a compiler built from master before #8844, and master's runs at b94c869 already showed both reds.

The W547 branch of the packed-array index emission wrote $signed( and ) whenever the element type is signed. Its sibling branches already check in_lvalue. One line:

let elem_signed = Self::type_is_signed(&elem_type) && !self.in_lvalue;

Both the opening and the closing parenthesis hang on that variable, so both go away on a target. compiler.rs is +1/-1 (the foreign-line budget holds), and FROZEN_HASH is t27c frozen-digest of the changed file.

Measured

  • t27c gen-verilog over all 2830 tracked .t27 files, old compiler against new: 25 specs change, 118 lines in total, and every changed line is exactly the removal of that wrapper before = / <= (checked line by line, not sampled).
  • specs/fpga/systolic.t27 with the new compiler: yosys read_verilog -sv -DSIMULATION; hierarchy -top fpga_systolic exit 0; iverilog -g2012 -DSIMULATION exit 0; t27c test-report 6/6, 0 vacuous.
  • Seals: 20 specs re-saved (26 seal files with their twins), only gen_hash_verilog moved, all 26 verify MATCH with the final compiler.

What is NOT done, and why

specs/ml/host_io_model.t27 is one of the 25 specs, but its seal (.trinity/seals/ml_host_io_model.json) is not re-saved. Its host file I/O glue is Linux-only (__t27_host_ret takes the usize that Linux's raw open returns; on macOS Zig's libc open returns c_int and is variadic), so the spec does not compile on the Mac this change was made on, and t27c seal --save refuses to re-save a seal that records a pass (--force would record this Mac's failure as the spec's truth, which it is not). That one hash (gen_hash_verilog) needs a single t27c seal specs/ml/host_io_model.t27 --save on a Linux machine (the lab) at this PR's head. Until then coverage and spec-guards will name that one seal.

The fix also changes the output of the three specs that have no seal (local_arrays fixture, systolic, gen_w682); nothing to re-save there.

🤖 Generated with Claude Code

@claude
gen-verilog: do not wrap an assignment target in $signed (Closes #10780)
b33239e 
A packed signed array element on the left of an assignment was emitted as $signed(c[...]) = ..., which is not a legal Verilog assignment target (yosys: unexpected TOK_TO_SIGNED; iverilog: syntax error). specs/fpga/systolic.t27 (#7719) hit it, which made fpga-lint (1/60 modules) and fpga-conformance (NEW systolic: 2 errors) red on master. The W547 branch of the packed-array index emission wrote the wrapper unconditionally; the sibling branches already check in_lvalue. One line: elem_signed is false while the target is being emitted, so both the opening and the closing parenthesis go away.

Measured: t27c gen-verilog over all 2830 tracked .t27 files, before and after: 25 specs change, 118 lines in total, and every changed line is exactly the removal of that wrapper before the assignment operator (checked line by line). systolic.t27 now passes yosys read_verilog -sv; hierarchy and iverilog -g2012 -DSIMULATION, tests 6/6, 0 vacuous. Seals: 20 specs re-saved (26 seal files with twins), only gen_hash_verilog moved, all verify MATCH. NOT re-saved: specs/ml/host_io_model.t27. Its host file I/O glue is Linux-only (a usize-returning open), so it does not compile on macOS and t27c seal refuses to re-save it there; its gen_hash_verilog needs one t27c seal --save on a Linux machine. FROZEN_HASH is the frozen-digest of the changed compiler.rs; compiler.rs is +1/-1, check_budget passes.

Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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gHashTag commented Oct 19, 2026

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Request for whoever runs the Linux lab (t27c-lab / the steward): one command on this PR's head, so the PR can land.

Need: re-save one seal that cannot be made on macOS. specs/ml/host_io_model.t27 is one of the 25 specs whose Verilog changes (the $signed(...) wrapper on an assignment target is gone), but its host file I/O glue is Linux-only, so t27c seal refuses it on a Mac. Its gen_hash_verilog is the only hash that moved; the other 25 seal files are already re-saved here and verify MATCH.

git fetch origin fix/gen-verilog-signed-lvalue-10780 && git checkout FETCH_HEAD
cargo build --release -p t27c
./target/release/t27c seal specs/ml/host_io_model.t27 --save
./target/release/t27c seal --verify specs/ml/host_io_model.t27     # expect: all hashes MATCH
git add .trinity/seals/ml_host_io_model.json && git commit -m "seal: re-save ml_host_io_model with the signed-lvalue fix (Closes #10780)" && git push origin HEAD:fix/gen-verilog-signed-lvalue-10780

Default if nobody answers: the PR waits, and I chase once in two hours. Without that seal, coverage and spec-guards name exactly one seal (ml_host_io_model.json, gen-drift) on this PR; the merge rules treat that as the PR's own red, so it does not merge on its own.

Meanwhile: I keep it up to date with master and watch it.

Measured facts, commands and the line-by-line check of all 118 changed lines are in the PR description.

🤖 Generated with Claude Code

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PR Dashboard

Generated at: 2026-10-19 16:24:30 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 43
PRs with All Checks Green 7
READY 2
FAILING 43
PENDING 0
NO CHECKS YET 0

These columns do not partition: 2 + 43 + 0 + 0 = 45, and there are 50 open PRs. A PR is being counted twice or not at all.

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=e34e1b174c96 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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gHashTag enabled auto-merge (squash) October 19, 2026 16:24
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gHashTag merged commit fcb3bc5 into master Oct 19, 2026
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@gHashTag @claude
elab baseline: add systolic 0 (Closes #11099) (#11100)
b57deed 
#11094 made specs systolic generate Verilog that iverilog elaborates with
0 errors. The ratchet reads a generated module absent from the baseline as
NEW and fails, even at 0: master's fpga-conformance has been red on
fcb3bc5 with "elaboration errors: 214 (baseline 214)" and
"NEW systolic: 0 errors, not in baseline".

Produced by tools/check_elab_ratchet.py --update-baseline on a t27c with
master's compiler.rs digest (e34e1b174c96, == FROZEN_HASH); the verify run
matched CI's numbers exactly. The calibration comment stays iverilog 12.0
(CI's version): every other count is identical under 13.0.

Co-authored-by: Claude <claude@anthropic.com>
Co-authored-by: Claude Sonnet 5.5 <noreply@anthropic.com>
This was referenced Oct 19, 2026
Closed
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Open
gHashTag added a commit that referenced this pull request Oct 19, 2026
@gHashTag @claude
seals: ml_host_io_model gen_hash_verilog follows the gen-verilog assi…
9a22e46 
…gnment-target fix (Closes #11102) (#11105)

specs/ml/host_io_model.t27 is unchanged and gen_hash_zig, gen_hash_c, gen_hash_rust still MATCH; only the Verilog hash moved (#11094). t27c seal --save refuses on macOS for this spec (#11103), so the one value was set to what t27c computes; the recorded 3 of 3 test pass stays valid because the Zig it ran is byte-identical. t27c seal --verify prints no MISMATCH and tools/check_seal_currency.py exits 0.

Co-authored-by: Claude <claude@anthropic.com>
Co-authored-by: Claude Sonnet 5.5 <noreply@anthropic.com>
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[bug] gen-verilog lowers an assignment to a signed array element as $signed(c[..]) = .., an illegal l-value (master FPGA E2E red since #7719)

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