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Add origin-latency hints, origin-aware sparse gather policy and a 256 KiB default coalescing gap for high-latency origins. Share reusable small columns through Arc handles and a Weak registry. Store them in the ordinary index cache; eviction removes the cache entry while live handles retain the allocation. Auto admission uses the backend's ordinary maximum entry size.
Dependencies
Depends on #9834, #9833. The base branch
yang/layered-rq-residency-baseonly merges these prerequisite heads so this PR shows its own feature diff. After the prerequisites land, rebase this PR’s own feature commit onto main (including after squash merges), then retarget it to main. Do not use the review-base branch as the final merge destination.Integrated Lance main
b3c8619886b9and the updated 3–9-bit layered prerequisites. Standalone benchmark/POC tools remain excluded.An Arc handle is acquired before remapping or cache lookups can promote other entries, so eviction during index open cannot force a reload of a live store. Both legacy and tagged row-ID remapping remain wired through index open and reconstruction; main's pairwise readers are retained.
Validation
This PR tree passed formatting and full-workspace clippy (--all --tests --benches -- -D warnings, Rust 1.98.1, Linux x86_64). The integrated composition passed 670 BQ tests and 22 layered integration tests on x86_64, plus 22 layered and 111 lazy/resident integration tests on macOS arm64. Production and Rust test source equality was verified after the final dependency refresh; the only later source change adds Java test coverage.
No new performance measurement is claimed. CI is not awaited.
Tracking
OSS-2563