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t27c: accept uN casts, 1 <= N <= 64, decided in int_type_names.t27 (Closes #10072) - #10084

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t27c: accept uN casts, 1 <= N <= 64, decided in int_type_names.t27 (Closes #10072)#10084
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Closes #10072. Part of epic #10066 (Build-A-Chip-Bench proxy run).

What changes

t27b uses t27c's parser unchanged, and that parser refused a cast into an odd unsigned width: x as u3 and x as u12 failed with "unknown cast target type". Odd widths already worked in params and returns (fn f(x: u12) -> u12, #5904). Only the cast was missing.

  • The decision is t27. specs/compiler/int_type_names.t27 gains uint_bits(ty) -> ?u32. It returns N for uN with 1 <= N <= 64 and no leading zero, and null for everything else. zig_uint_bits now defers to it past usize, so the Zig reference narrows with @truncate, as t27b verilog's t27_uN does. (@intCast would panic on 13 as u3.)
  • The Rust is generated. bootstrap/gen/rust/compiler/int_type_names.rs is t27c gen-rust output, regenerated on the lab. A second gen-rust with the patched binary produced the same bytes (fixed point).
  • Hand-written Rust: 3 lines added, 3 removed, all in bootstrap/src/compiler.rs.
    • The VALID_CAST_TYPES check also accepts int_type_names::uint_bits(..).is_some().
    • The doc line now names x as u0 as the refused example and points at the spec.
    • The error text adds "or uN, 1 <= N <= 64".
    • bootstrap/stage0/FROZEN_HASH is resealed. foreign-budget and own-language pass, with no --no-verify.
  • New conformance spec specs/tri/t27b/conformance/verilog_odd_cast.t27, 4 tests:
    • the 8-sample moving average from the proxy run: u12 samples, a sum formed in u32, then as u12;
    • as u3 and as u1 keep the low bits;
    • u12 to u16 is a zero fill, and u12 to u8 keeps the low byte;
    • a narrowing inside on_clock.
  • odd_width_int.t27 header points at the new spec. There are 3 seals, and one ledger row in docs/reports/t27b_expectations.json.

Evidence (Railway lab, never the Mac)

  • t27c test-report, 0 vacuous passes in each:
    • int_type_names: 6/6;
    • verilog_odd_cast: 4/4;
    • odd_width_int: 9/9.
  • Negative controls (parse):
    • as u1, as u3, as u12 and as u64 exit 0;
    • as u0, as u65, as u3x, as u012 and as banana exit 1 with "unknown cast target type";
    • the spec's tests also refuse u99, u128, u00, u, U3, i3, x3, u 3, u-3, usize and bool.
  • Mutation controls: each of 5 mutants of uint_bits fails at least one test:
    • upper bound changed to 65;
    • upper bound changed to 99;
    • leading-zero check broken;
    • u prefix check broken;
    • digit check removed.
  • t27b verilog on the new spec emits:
    • function [11:0] avg8 with input [11:0] for each of its 8 args;
    • narrowing through t27_u12(...), t27_u3(x) and t27_u1(x).
    • The Icarus testbench (-DT27B_TESTBENCH) reports "4 passed, 0 failed, 4 tests, 15 runtime asserts".
  • Sonnet receipt from the proxy run:
    • As written (-> u16 on a u12 average) it is still refused with a type mismatch, which is correct.
    • With -> u12 and as u12 it gives exit 0 and output reg [11:0] data_out; Icarus reports "2 passed, 0 failed".
  • Corpus diff (FR-004): all 2097 tracked specs were run through gen, gen-verilog, gen-rust and gen-c, pristine master ee3da59 against this branch. Result: 0 outputs differ. No existing spec casts from an odd width, so the @intCast to @truncate change touches only new code.
  • Other backends: gen-c and gen-rust still pass u3 through as a type name. A host compiler refuses it loudly; nothing is silently miscompiled. Lowering those is out of scope.

Not verified here

  • Native t27b (arm64 JIT) was not run. The x86 lab cannot run it, and an aarch64 cross-link of t27b failed on a linker flag.
    • The new ledger row says pass. That is a prediction from the passing t27b verilog bench and the native odd_width_int row.
    • t27b-native-ratchet (not required, Q16) is the check. If it reports an UNEXPECTED FAILURE, the row or t27b's JIT cast lowering needs a follow-up.
  • Keyword-named ports are out of scope; another session handles them.

🤖 Generated with Claude Code

@gHashTag @claude
t27c: accept uN casts, 1 <= N <= 64, decided in int_type_names.t27 (C…
c6d42c0 
…loses #10072)

`x as u3` and `x as u12` were refused at parse time by a hand-written
whitelist in compiler.rs. The decision now lives in
specs/compiler/int_type_names.t27 (`uint_bits`, with tests and negative
controls: u0, u65, u012, u3x, banana stay refused). The parser consults the
generated copy; zig_uint_bits defers to it past usize, so the reference
truncates a narrowing cast exactly as t27b verilog's t27_uN does.

Hand-written Rust: 3 lines added, 3 removed, in compiler.rs (the call site,
the doc line, the error text). FROZEN_HASH resealed.

New conformance spec verilog_odd_cast.t27 carries the Build-A-Chip-Bench
moving average (u12 samples, `as u12`), narrowing and widening casts, and a
module-level narrowing in on_clock. Refs #10066.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@gHashTag gHashTag added the owner-approved-foreign Owner-approved exception to the only-t27 rule: hand-written foreign code allowed in this PR label Oct 17, 2026
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  • ⚠️ STALE -- sha256(compiler.rs)=3b53d48ddb52 != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

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gHashTag merged commit 0a09094 into master Oct 17, 2026
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gHashTag added a commit that referenced this pull request Oct 18, 2026
@gHashTag @claude
t27c: rejects_invalid_width test uses u65, u3 is a legal cast since #…
910bced 
…10084 (Closes #10320) (#10322)

Co-authored-by: Claude Sonnet 5.5 <noreply@anthropic.com>
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t27c: accept as uN (1 <= N <= 64) as a cast target, so t27b verilog can narrow to odd widths

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