Skip to content

fpga(ax7203): rc_filter without Verilog real -- f64 references in the tests, comptime_float PLL params (Closes #10294) - #10296

Merged
gHashTag merged 1 commit into
masterfrom
fix/rc-filter-lint-10276
Oct 18, 2026
Merged

fpga(ax7203): rc_filter without Verilog real -- f64 references in the tests, comptime_float PLL params (Closes #10294)#10296
gHashTag merged 1 commit into
masterfrom
fix/rc-filter-lint-10276

Conversation

@gHashTag

@gHashTag gHashTag commented Oct 18, 2026

Copy link
Copy Markdown
Owner

Closes #10294

#10278 (the cpphdl RC low-pass on the AX7203) was auto-merged by issue-gate at its first commit, before its own red checks were fixed. This PR takes back what that spec brought to master.

Changes

  • specs/fpga/rc_filter_ax7203.t27
    • The f64 helpers fabs, volts and be_charge are gone from module level. t27c gen-verilog emitted them as function real, and yosys read_verilog -sv refuses that (TOK_REAL).
    • The f64 backward-Euler references now run inline in the tests and are compared as squares (|d| < t is d * d < t * t). The bounds are unchanged: under 3 LSB against f64, cpphdl's 0.992396 V at 5 us, and step halving converging toward the analytic value.
    • PLLE2_ADV's CLKIN1_PERIOD and REF_JITTER1 are now comptime_float. As f64 they were emitted as input real, the same TOK_REAL.
    • The clocked machine is unchanged.
  • .trinity/seals/fpga_FpgaRcFilter.json: resealed on the Railway lab for the new spec (spec_hash 3728871b…).
  • tools/duplicate_bodies_baseline.txt: blesses hex_digit 2. The second copy is in ddr3_head_bandwidth.t27. It is deliberate: t27b bitstream specs are self-contained, and no fpga spec imports another.
  • tools/elab_baseline.txt
    • Adds rc_filter_ax7203 8 with a KNOWN GAP note. t27c gen-verilog has no lowering for pin attributes or primitive instances:
      • 3 pins come out as undefined;
      • IBUFDS, PLLE2_ADV, BUFG and IBUF come out as localparams with a function call (one of those errors is the PLL feedback, read as a recursive parameter).
    • The bitstream is built by t27b verilog, which lowers all of these.
    • Also adds 0 rows for openxc7_dsp_fabric, wasm_board_ax7203 and wasm_interp. They reached master without rows and elaborate clean, so the rows hide nothing.

Measured

Railway lab:

Board (ALINX AX7203):

  • New bitstream sha256 e619e9667fd9627b9026d56bd03bfb535c9aff0a81f14f8f11e7ae777f56b392, flashed with openFPGALoader -c digilent_hs2 --busdev-num 1:3.
  • 2130 of 2130 consecutive UART lines (counter L=0x1E08..0x2659, no gaps) read A=FE0DA3 B=1EE92 S=77EDFF0295C3FE9E C=4B0 PASS.

Still red, said plainly

  • fpga-lint still fails on rc_filter_ax7203.v:91, "Non-constant function call in constant expression". That line is the IBUFDS instance as t27c emits it. ddr3_head_bandwidth.v:94 fails the same way on master.
    • No spec-side shape fixes this without dropping the primitives the bitstream needs.
    • The real fix is primitive-instance lowering in t27c gen-verilog, which is compiler code and outside this PR.
  • duplicate-bodies on master also names buf_has, digit_byte, put_count, put_str, str_eq and bytes_eq. They come from other specs and are not touched here.
  • t27b-native-ratchet: ddr3_head_bandwidth.t27 is listed as pass but is blocked under t27b. It is left to that spec's owner. rc_filter_ax7203 passes there on arm64.

🤖 Generated with Claude Code

@gHashTag @claude
fpga(ax7203): rc_filter without Verilog real -- f64 references in the…
e9b1425 
… tests, comptime_float PLL params (Closes #10294)

#10278 merged at its first commit, before its own reds were fixed:

- fpga-lint: t27c gen-verilog emits a module-level f64 fn as
  `function real` and an f64 param as `input real`; yosys read_verilog
  -sv refuses both (TOK_REAL). The f64 backward-Euler references now run
  inline in the tests, compared as squares, and PLLE2_ADV takes
  comptime_float. Same bounds as before; the clocked machine is unchanged.
- duplicate-bodies: hex_digit blessed (the copy in ddr3_head_bandwidth
  is deliberate, t27b bitstream specs are self-contained).
- elab ratchet: rc_filter_ax7203 8 recorded as a KNOWN GAP (t27c has no
  lowering for pin attributes or primitive instances; t27b builds the
  bitstream), plus 0 rows for three modules master added without one.

Lab: 10/10 tests, 0 vacuous; seal spec_hash 3728871b. t27b top.v logic
same as the board-verified build. Board: bitstream e619e966, 2130 of
2130 consecutive lines PASS.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@gHashTag
gHashTag enabled auto-merge (squash) October 18, 2026 07:52
@github-actions

github-actions Bot commented Oct 18, 2026

Copy link
Copy Markdown
Contributor

PR Dashboard

Generated at: 2026-10-18 07:53:04 UTC

Summary

Status Count
Total Open PRs 50
PRs with Failing Checks 50
PRs with All Checks Green 0
READY 0
FAILING 50
PENDING 0
NO CHECKS YET 0

Seal Status

  • ⚠️ STALE -- sha256(compiler.rs)=0f8c66b9ed0e != manifest seal=87e5cbd3ad94.
    The committed NMSE numbers were certified against an older compiler.rs.
    Run scripts/reseal-check.sh locally for the two-step reseal command (advisory; not a merge gate).

@gHashTag
gHashTag merged commit b8e3288 into master Oct 18, 2026
29 of 32 checks passed
This was referenced Oct 18, 2026
Closed
Merged
Closed
Merged
gHashTag added a commit that referenced this pull request Oct 18, 2026
@gHashTag @claude
fpga(ax7203): rc_filter PLL params back to f64 so t27b passes the spe…
97bb27f 
…c again (Closes #10313) (#10314)

master's t27b-native-ratchet reads `specs/fpga/rc_filter_ax7203.t27:
ledger pass, now blocked: type comptime_float`. #10278 ledgered the spec
as t27b pass; #10296 then typed PLLE2_ADV's CLKIN1_PERIOD and
REF_JITTER1 as comptime_float so t27c gen-verilog would not emit
`input real`, and t27b rejects a comptime_float parameter. #10302 made
gen-verilog skip t27b bitstream specs, so that reason is gone: the two
parameters go back to f64 and the doc comment says why.

Measured on the Railway lab at master 9da2c5f, t27b and t27c built
there:
- t27b on master's spec: "unsupported construct type comptime_float at
  line 247"; on this spec: accepted, and `t27b build --elf` writes the
  object (the x86 lab has no t27b JIT; CI's arm64 runs the tests).
- `t27b verilog`: same 608 lines as master's; only the five
  `// ... (line N)` comments move by 2. The PLL instance still reads
  CLKIN1_PERIOD(5.0), REF_JITTER1(0.01), so the board RTL does not
  change.
- reference (t27c test-report, zig 0.16.0): 10 of 10 pass, 0 vacuous.
- seal regenerated with `t27c seal --save`: spec_hash 8fba8a41.

Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
This was referenced Oct 18, 2026
Open
Closed
Merged
gHashTag added a commit that referenced this pull request Oct 19, 2026
@gHashTag @claude
ci(dupe-ratchet): record the seven widget-logic helper copies as deli…
b24015f 
…berate (Closes #11013) (#11014)

Master was red on duplicate-bodies since b92f6f1 (#10965): digits_val,
ws_at, ws_back, ws_before, ws_fwd, ws_len_at and ws_len_before each exist
twice across the widget logic ports (lut_explain/lut_treemap,
fasm_skyline/stat_card/lut_depth). The earlier hex_digit copy named in the
first brief was already removed by #10296.

Each widget logic spec compiles to its own wasm module with module-level
state, so a cross-module use is a design change that belongs to the widget
epic (#10937), not to a red-master fix. The copies are recorded with
python3 tools/dupe_scan.py --bless, run on the Railway lab: exactly seven
lines added, dupe_scan exits 0 after, and a new duplicate still fails.

Co-authored-by: Claude Sonnet 5.5 <noreply@anthropic.com>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

No reviews

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

fpga(ax7203): take back the reds rc_filter brought to master (TOK_REAL, hex_digit, elab ratchet)

1 participant

@gHashTag