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…creen on the pin, feasibility note (Refs #10782) specs/fpga/t27os_uart_shell_ax7203.t27 reuses t27os::pane_state, agents and vt by `use`: four panes advanced by the real pane_step, a VT100 screen sent on the UART, keys and a script as events. 8 run-time tests pass on the lab, the RTL lowers (t27b verilog) and yosys synthesises it (about 468 LCs). No bitstream: the lab has no nextpnr-xilinx or fbg484 chipdb. See the note. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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…nd an 8x8 scanout, pin-free until the connector is confirmed (Refs #10782) specs/fpga/vga_text_core.t27: the timing and text scanout, 7 run-time tests pass on the lab, lowers to Verilog, yosys synthesises it. No pins: the connector is not established in the repository. The feasibility note lists the two routes the owner must choose between. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
This was referenced Oct 19, 2026
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This was referenced Oct 19, 2026
… FPGA TMDS -- pin table (second-hand, cited) and what is missing (Refs #10782) The TMDS-in-t27 route has no pins to drive on this board. The feasibility note now records the parallel-bus route, the sourced pin table and its caveats. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
This was referenced Oct 19, 2026
…hem against the T27 OS frame, in t27 only (Refs #10782) specs/fpga/hdmi_grab.t27: the device picker reads ffmpeg's avfoundation list and skips FaceTime, OBS Virtual, Capture screen and iPhone; the checker samples a grabbed PPM against vga_text_core's own pixel_at (title on black) and gives a verdict per frame. main starts ffmpeg through fork/execve, retries every 5 s with a clear no-device message, and prints PASS or FAIL per frame. 14 tests on the lab (zig test of the t27c output): device lists with and without a dongle, pass at 640x480 and 1280x720, negative controls (black, white, inverted, shifted, lit square, truncated, not a PPM). The binary builds with zig build-exe -lc and takes the no-device path on the lab. Not run against a real dongle: macOS lists no capture device today. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-10-19 09:15:11 UTC
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This was referenced Oct 19, 2026
…l pp. 31-32, with file hash and source (Refs #10782) All 29 balls (24 data, clk, de, hs, vs, reset) equal the second-hand table. The two I2C balls are not in the manual text and stay second-hand. The PDF is not committed (licence); the record names file, size, sha256 and source. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
… pin-define sheet, with hash and source (Refs #10782) The schematic package is not committed. CI2CA strap and the SiI9134 register sequence stay open. Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
…- DIFF_SSTL15 clock, SRAM-only load, placed-pin readback, IDCODE revision nibble (Refs #10782) Co-Authored-By: Claude Sonnet 5.5 <noreply@anthropic.com>
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PR DashboardGenerated at: 2026-10-19 09:54:22 UTC
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This was referenced Oct 20, 2026
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This was referenced Oct 20, 2026
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Refs #10782. Depends on #10783 (the
specs/t27os/files are not on master yet), so this is a draft.What
docs/fpga/T27OS_ON_FPGA_FEASIBILITY.md: which T27 OS specs are pure logic and can be lowered, which are host-bound and what replaces them on the board, the AX7203 I/O (UART used; Ethernet via the existing eth cells; HDMI not established), and a staged plan. Each classification is marked measured, read, or not established.specs/fpga/t27os_uart_shell_ax7203.t27: T27 OS over UART. Four panes advanced by the realpane_stepfromt27os::pane_state(plusagentsconstants), a VT100 screen sent on the UART TX pin, keys on the RX pin and a script as events.t27os::vtis used by the spec's tests to read the screen back as cells.docs/reports/t27b_expectations.json: entry for the new spec.Measured on the Railway lab
t27c test-reportis blocked there because zig is not on PATH).uart_txpin and compares all 259 bytes of a frame to the screen function.>marker, a script step, and the line-length function are each caught. Mutating the RX sample offset (1 bit-time instead of 1.5) is NOT caught; the RX timing check is weak.t27b veriloglowers it (1074 lines); yosyssynth_xilinxfor xc7 passes with 0 problems: 1274 cells, about 468 LCs, 272 flip-flops.Not done (blocked, nothing faked)
nextpnr-xilinx, noxc7a200tfbg484-2chipdb and no prjxray database. The openXC7 tools exist on the Mac, where heavy runs are barred.openFPGALoader --scan-usbshowed no device.Expect red until #10783 lands
The
use t27os::...imports resolve only with the T27 OS specs, so the t27b corpus check on master alone cannot pass this spec.🤖 Generated with Claude Code